ak4382a AKM Semiconductor, Inc., ak4382a Datasheet
ak4382a
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ak4382a Summary of contents
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... ASAHI KASEI The AK4382A offers the perfect mix for cost and performance based audio systems. Using AKM's multi bit architecture for its modulator the AK4382A delivers a wide dynamic range while preserving linearity for improved THD+N performance. The AK4382A has full differential SCF outputs, removing the need for AC coupling capacitors and increasing performance for systems with excessive clock jitter ...
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... Audio Serial Data Clock Pin Audio Serial Data Input Pin L/R Clock Pin Power-Down Mode Pin When at “L”, the AK4382A is in the power-down mode and is held in reset. The AK4382A should always be reset upon power-up. Chip Select Pin Control Data Input Pin ...
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... Note 1) Parameter Power Supply *AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS0071-E-02 ABSOLUTE MAXIMUM RATINGS Symbol min VDD -0.3 IIN - VIND -0.3 Ta -40 Tstg -65 Symbol min VDD 4. [AK4382A] max Units 6 VDD+0 150 C typ max Units 5.0 5.25 V 2002/12 ...
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... All digital inputs in cluding clock pins (MCLK, BICK and LRCK) are held VDD or VSS. MS0071-E-02 ANALOG CHARACTERISTICS 2k ; unless otherwise specified) L min (Note 3) 0dBFS -60dBFS 0dBFS -60dBFS 0dBFS -60dBFS (Note 4) 102 (Note 5) 102 90 (Note 6) 2.55 (Note 7) 2 (Note [AK4382A] typ max Units 24 Bits -94 - -92 - ...
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... +0/ -0.6 Symbol min 18 CHARACTERISTICS Symbol min VIH 2.2 VIL - VOH VDD-0.4 VOL - Iin - - 5 - [AK4382A] typ max Units 20.0 kHz - kHz kHz 0. 1/ typ max Units 8.1 kHz - kHz kHz 0.005 1/ typ max ...
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... CSN “ ” to CCLK “ ” CCLK “ ” to CSN “ ” Reset Timing PDN Pulse Width (Note 13) Notes : 12. BICK rising edge must not occur at the same time as LRCK edge. 13. The AK4382A can be reset by bringing PDN= “L”. MS0071-E-02 SWITCHING CHARACTERISTICS Symbol min fCLK 2 ...
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... Timing Diagram MCLK tCLKH LRCK BICK tBCKH LRCK tBLR BICK SDTI MS0071-E-02 1/fCLK tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs tBCK tBCKL Clock Timing tLRB tSDS tSDH Serial Interface Timing - 7 - [AK4382A] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 2002/12 ...
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... CCLK CDTI C1 CSN CCLK CDTI D3 PDN MS0071-E-02 tCCKL tCCKH tCDS tCDH C0 R/W WRITE Command Input Timing WRITE Data Input Timing tPD Power-down Timing - 8 - [AK4382A] VIH VIL VIH VIL VIH A4 VIL tCSW VIH VIL tCSH VIH VIL VIH VIL VIL 2002/12 ...
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... Register 00H), the sampling speed is set by DFS0/1(Table 1). The frequency of MCLK at each sampling speed is set automatically. (Table 2~4).After exiting reset (PDN = “ ”), the AK4382A is in Auto Setting Mode. In Auto Setting Mode (ACKS = “1”: Default), as MCLK frequency is detected automatically (Table 5), and the internal master clock becomes the appropriate frequency (Table 6 not necessary to set DFS0/1 ...
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... LSB Justified 0 1 20bit LSB Justified 1 0 24bit MSB Justified 24bit I S Compatible 0 0 24bit LSB Justified Table 7. Audio Data Formats - 10 - [AK4382A] Sampling Speed 768fs 24.5760 Normal 33.8688 36.8640 - Double - - Quad - BICK Figure 32fs Figure 1 40fs Figure 2 48fs ...
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... Don’t care Don’t care Figure 2. Mode 1,4 Timing Don’t care 23 22 Figure 3. Mode 2 Timing - 11 - [AK4382A Rch Data ...
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... Table 8. De-emphasis Filter Control (Normal Speed Mode) n Output Volume The AK4382A includes channel independent digital output volumes (ATT) with 256 levels at linear step including MUTE. These volumes are in front of the DAC and can attenuate the input data from 0dB to –48dB and mute. When changing levels, transitions are executed via soft changes ...
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... ASAHI KASEI n Zero Detection The AK4382A has channel-independent zeros detect function. When the input data at each channel is continuously zero s for 8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin of each channel immediately goes to “L” if input data of each channel is not zero after going DZF “H”. If RSTN bit is “0”, DZF pins of both channels go to “ H”. DZF pin of both channels go to “ ...
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... The AK4382A should be reset once by bringing PDN= ”L” upon power-up. The AK4382A is powered up and the internal timing starts clocking by LRCK “ ” after exiting reset and power down state by MCLK. The AK4382A is in the power-down mode until MCLK and LRCK are input. ...
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... There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2~3/fs from RSTN bit “1” to the internal RSTN “1”. MS0071-E-02 3~4/fs (6) 2~3/fs (6) Digital Block Power-down “0” data GD (3) (2) (3) (4) Don’t care ”) of the internal timing of RSTN bit. This noise is output even if “0” data is Figure 7. Reset Sequence Example - 15 - [AK4382A] Normal Operation GD (1) 2/fs(5) 2002/12 ...
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... C1 C0 R/W *The AK4382A does not support the read command and chip address. C1/0 and R/W are fixed to “011” *When the AK4382A is in the power down mode (PDN = “L”) or the MCLK is not provided, writing into the control register is inhibited. n Register Map Addr ...
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... RSTN: Internal timing reset control 0: Reset. All registers are not initialized. 1: Normal Operation When MCLK frequency or DFS change s , the AK4382A should be reset by PDN pin or RSTN bit. PW: Power down control 0: Power down . All registers are not initialized. 1: Normal Operation DIF2-0: Audio data interface formats (see Table 7) Initial: “ ...
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... DZFR 15 3 SDTI VDD 14 4 LRCK VSS 13 AK4382A 5 PDN AOUTL CSN AOUTL- 11 CCLK 7 AOUTR CDTI AOUTR- 9 Figure 9. Typical Connection Diagram - 18 - [AK4382A DZFB ATT2 ATT1 ATT0 ATT2 ATT1 ATT0 Analog + Supply 5V 10u 0.1u Lch ...
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... When R1=200 1k fc=93.2kHz, Q=0.712, g=-0.1dB at 40kHz When R1=180 fc=98.2kHz, Q=0.681, g=-0.2dB at 40kHz 4.7k 4.7k R1 470p +Vop 3300p 4.7k R1 -Vop 4.7k 470p When R1=200 fc=93.2kHz, Q=0.712, g=-0.1dB at 40kHz When R1=180 fc=98.2kHz, Q=0.681, g=-0.2dB at 40kHz - 19 - [AK4382A positive full scale for 7FFFFF AOUT Analog Out Analog Out 2002/12 ...
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... TSSOP (Unit: mm) *5.0 0 0.22 0.1 0.13 M Seating Plane NOTE: Dimension "*" does not include mold flash. n Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: MS0071-E-02 PACKAGE 0.65 Detail A 0.10 Epoxy Cu Solder(Pb free) plate - 20 - [AK4382A] 1.05 0.05 0.17 0.05 0.1 0.1 0-10 2002/12 ...
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... AKM harmless from any and all claims arising from the said product in the absence of such notification. MS0071-E-02 MARKING AKM 4382AT XXYYY 1) Pin #1 indication 2) Date Code : XXYYY (5 digits) XX: Lot# YYY: Date Code 3) Marketing Code : 4382AT 4) Asahi Kasei Logo IMPORTANT NOTICE - 21 - [AK4382A] 2002/12 ...