tc59lm906amg TOSHIBA Semiconductor CORPORATION, tc59lm906amg Datasheet - Page 12

• Manufacturer Part Number: tc59lm906amg
• Description: Mos Digital Integrated Circuit Silicon Monolithic
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Command
Address
(10)
V
DQS
DQS
V
POWER UP SEQUENCE
Notes:
CLK
CLK
V
DDQ
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
DQ
REF
PD
DD
(1)
(2)
(3)
(4)
As for PD , being maintained by the low state ( 0.2 V) is desirable before a power-supply injection.
Apply V
Apply V
Start clock (CLK, CLK ) and maintain stable condition for 200 s (min).
After stable power and clock, apply DESL and take PD =H.
Issue EMRS to enable DLL and to define driver strength with OCD calibration mode exit command
(A7 A9 0). (Note: 1, 2)
Issue MRS for set CAS latency (CL), Burst Type (BT), and Burst Length (BL). (Note: 1)
Issue two or more Auto-Refresh commands (Note: 1).
Ready for normal operation after 200 clocks from Extended Mode Register programming.
If OCD calibration (Off Chip Driver impedance adjustment) is used, execute OCD calibration sequence.
Sequence 6, 7 and 8 can be issued in random order.
L Logic Low, H
All DQs output level are high impedance state during power up sequence.
Set DQS mode for TC59LM906AMG.
200us(min)
DD
DDQ
before or at the same time as V
before or at the same time as V
t
PDEX
Hi-Z
Hi-Z
Logic High
DESL
1.5V or 1.8V(TYP)
1/2 V
l
PDA
2.5V(TYP)
RDA MRS DESL
DDQ
EMRS
(TYP)
op-code
EMRS
l
RSC
DDQ
REF
RDA MRS
.
.
MRS
op-code
MRS
l
RSC
DESL WRA REF
200clock cycle(min)
TC59LM914/06AMG-37,-50
DESL
l
REFC
Auto Refresh cycle
WRA REF
2004-08-20 12/59
DESL
l
REFC
Normal Operation
Rev 1.0