ata5749-6dq ATMEL Corporation, ata5749-6dq Datasheet - Page 13

• Manufacturer Part Number: ata5749-6dq
• Description: Fractional-n Pll Transmitter Ic
• Manufacturer: ATMEL Corporation

6.2
Figure 6-1.
Figure 6-2.
9128D–RKE–01/09
Programming
SDIN_TXDIN
SDIN_TXDIN
CLK (Output)
SCK (Input)
PA (Output
EN (Input)
SPI Bus Timing
Timing Diagram if Register Programming is Faster than T
Power)
(Input)
SCK
EN
OFF_
Mode
The configuration register is programmed serially using the SPI bus, starting with the MSB. It
consists of the Enable line (EN), the Data line (SDIN_TXDIN), and the SPI-Bus Clock (SCK).
The SDIN_TXDIN data is loaded on the positive edge of the SCK. The contents of the configura-
tion register become programmed on the negative SCK edge of the last bit (LSB) of the
programming sequence. The timing of this bus is shown in
usable clock speed on the SPI bus is limited to 2 MHz.
At the conclusion of the 32 bit programming sequence, the SDIN_TXDIN line becomes the mod-
ulation input for the RF transmitter. After programming is complete, the SCK signal has no effect
on the device. To disable the transmitter and enter the OFF Mode, EN and SDIN_TXDIN must
be returned to the LOW state. For clarity, several additional timing diagrams are included.
6-2
shows the situation when the programming terminates faster then the XTO is ready.
T
T
Setup
EN_setup
Start_Up_
Mode_1
MSB
T
T
Hold
SCK_High
32-bit Configuration
T
XTO
Start_Up_
T
Mode_2
SCK_Cycle
X
T
SCK_Low
MSB-1
XTO
X
Mode1
T
TX_
PLL
ATA5749 [Preliminary]
X
X
TX_Mode1 and
Figure
TX_Mode2
TX_Mode2
TX-Data
FSK;
ASK:
T
SDIN_TXDIN_setup
6-1. Note that the maximum
X
OFF_Mode
Figure
13