m40z300 STMicroelectronics, m40z300 Datasheet - Page 9

• Manufacturer Part Number: m40z300
• Description: Nvram Controller For Up To Eight Lpsram
• Manufacturer: STMicroelectronics

2
Note:
Operation
The M40Z300/W, as shown in
parallel) standard low-power SRAMs. These SRAMs must be configured to have the chip
enable input disable all other input signals. Most slow, low-power SRAMs are configured like
this, however many fast SRAMs are not. During normal operating conditions, the
conditioned chip enable (E1
with timing shown in
connects V
When V
independent of E. In this situation, the SRAM is unconditionally write protected as V
below an out-of-tolerance threshold (V
associated with V
on page
shown in
In either case, THS pin must be connected to either V
If chip enable access is in progress during a power fail detection, that memory cycle
continues to completion before the memory is write protected. If the memory cycle is not
terminated within time t
protecting the SRAM. A power failure during a WRITE cycle may corrupt data at the
currently addressed location, but does not jeopardize the rest of the SRAM's contents. At
voltages below V
within the Write Protect Time (t
page
As V
battery to V
provides a voltage V
page
When V
E4
V
page
PFD
CON
CC
, independent of the E input, to allow for processor stabilization (see
10).
15).
16).
are held inactive for t
continues to degrade, the internal switch disconnects V
CC
CC
15. For the M40Z300W, the THS pin selects both the supply voltage and V
Table 6 on page
CC
degrades during a power failure, E1
rises above V
OUT
to V
. This occurs at the switchover voltage (V
PFD
PFD
OUT
OHB
Figure 6 on page 10
(min), the user can be assured the memory will be write protected
is selected by the Threshold Select (THS) pin and is shown in
. This switch has a voltage drop of less than 0.3V (I
WPT
SO
to the SRAM and can supply current I
15).
, E1
, V
CON
CER
OUT
Figure 5 on page
WPT
CON
to E4
(120ms maximum) after the power supply has reached
is switched back to the supply voltage. Outputs E1
) provided the V
to E4
CON
PFD
CON
) output pins follow the chip enable (E) input pin
and
). For the M40Z300 the power fail detection value
are unconditionally driven high, write
Table 7 on page
CON
8, can control up to four (eight, if placed in
CC
to E4
SS
fall time exceeds t
SO
or V
CON
). Below the V
OUT
are forced inactive
CC
OUT2
17. An internal switch
.
and connects the internal
(see
F
SO
OUT1
Table 6 on
Figure 10 on
(see
, the battery
).
Figure 6 on
PFD
CC
Table 6
CON
(also
falls
9/25
to