sx20ac Parallax, Inc., sx20ac Datasheet - Page 34

• Manufacturer Part Number: sx20ac
• Description: Configurable Communications Controllers With Ee/flash Program Memory, In-system Programming Capability And On-chip Debug
• Manufacturer: Parallax, Inc.

Parallax SX20AC/SX28AC
15.12.2.
When a return instruction is executed the subroutine stack
is popped. Specifically, the contents of Stack 1 are copied
into the program counter and the contents of each stack
level are moved to the next higher level. For example,
Stack 1 receives the contents of Stack 2, etc., until Stack 7
is overwritten with the contents of Stack 8. Stack 8 is left
unchanged, so the contents of Stack 8 are duplicated in
Stack 7.
15.13. Comparison and Conditional Branch
Instructions
The instruction set includes instructions such as
DECSZ fr (decrement file register and skip if zero),
INCSZ fr (increment file register and skip if zero),
SNB bit (bit test file register and skip if bit clear), and
© Parallax Inc.
Symbol
STATUS
PA2:PA0
OPTION
MODE
WDT
FSR
PC
DC
PD
TO
W
rx
fr
C
Z
k
!
f
Description
Working register
File register (memory mapped in range of 00h to FFh)
Lower eight bits of program counter (file register 02h)
STATUS register (file register 03h)
File Select Register (file register 04h)
Carry bit in STATUS register (Bit 0)
Digit Carry bit in STATUS register (Bit 1)
Zero bit in STATUS register (Bit 2)
Power Down bit in STATUS register (Bit 3)
Watchdog Timeout bit in STATUS register (Bit 4)
Page select bits in STATUS register (Bits7:5)
OPTION register (not memory mapped)
Watchdog Timer register (not memory-mapped)
MODE register (not memory mapped)
Port control register pointer (RA, RB, RC)
Non-memory-mapped register designator
File register address bit in opcode
Constant value bit in opcode
Pop Operation
Table 15-1: Key to Abbreviations and Symbols
Page 34 of 51
Symbol
addr12
addr8
addr9
<>
<<
>>
++
lit
--
n
b
#
&
^
SB bit (bit test file register and skip if bit set). These
instructions will cause the next instruction to be skipped if
the tested condition is true. If a skip instruction is
immediately followed by a PAGE or BANK instruction
(and the tested condition is true) then two instructions are
skipped and the operation consumes three cycles. This is
useful for conditional branching to another page where a
PAGE instruction precedes a JMP. If several PAGE and
BANK instructions immediately follow a skip instruction
then they are all skipped plus the next instruction and a
cycle is consumed for each.
15.14. Logical Instruction
The instruction set contain a full complement of the
logical instructions (AND, OR, Exclusive OR), with the
W register and a selected memory location (using either
direct or indirect addressing) serving as the two operands.
15.15. Shift and Rotate Instructions
The instruction set includes instructions for left or right
rotate-through-carry.
15.16. Complement and SWAP
The device can perform one’s complement operation on
the file register (fr) and W register. The MOV W,<>fr
instruction performs nibble-swap on the fr and puts the
value into the W register.
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Description
Numerical value bit in opcode
Bit position selector bit in opcode
File register / bit selector separator in assembly instruct.
Immediate literal designator in assembly instruction
Literal value in assembly language instruction
8-bit address in assembly language instruction
9-bit address in assembly language instruction
12-bit address in assembly language instruction
Logical 1’s complement
Logical OR
Logical exclusive OR
Logical AND
Swap high and low nibbles (4-bit segments)
Rotate left through carry bit
Rotate right through carry bit
Cecrement file register
Increment file register
Rev 1.6 11/20/2006
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