sx20ac Parallax, Inc., sx20ac Datasheet - Page 28

• Manufacturer Part Number: sx20ac
• Description: Configurable Communications Controllers With Ee/flash Program Memory, In-system Programming Capability And On-chip Debug
• Manufacturer: Parallax, Inc.

Parallax SX20AC/SX28AC
12.0 RESET
Power-On Reset, Brown-Out Reset, Watchdog Reset, or
External Reset initializes the device. Each one of these
reset conditions causes the program counter to branch to
the top of the program memory. For example, on the
device with 2048 K
memory, the program counter is initialized to 07FF upon
a valid reset condition.
The device incorporates an on-chip Power-On Reset
(POR) circuit that generates an internal reset as V
during power-up. Figure 12-2 is a block diagram of the
circuit. The circuit contains a 10-bit Delay Reset Timer
(DRT) and a reset latch. The DRT controls the reset
timeout delay. The reset latch controls the internal reset
signal.
Upon power-up, the reset latch is set (device held in
reset), and the DRT starts counting once it detects a valid
logic high signal at the MCLR pin. Once DRT reaches the
end of the timeout period (typically 72 msec), the reset
latch is cleared, releasing the device from reset state.
Figure 12-1 shows a power-up sequence where MCLR is
not tied to the V
© Parallax Inc.
DD
pin and V
($800 hex) words of program
DD
signal is allowed to rise
DD
rises
Page 28 of 51
and stabilize before MCLR pin is brought high. The
device will actually come out of reset T
The brown-out circuitry resets the chip when device
power (V
not to zero, and then recovers to the normal value.
MCLR goes high.
Figure 12-1: Time-Out Sequence on Power-Up
DD
) dips below its minimum allowed value, but
( MCLR not tied to V
Figure 12-2
Block Diagram
of On-Chip Reset Circuit
Note: Ripple counter is 10 bits for Power
on Reset (POR) only.
dd
Rev 1.6 11/20/2006
)
www.parallax.com
DRT
msec after