w77e58 Winbond Electronics Corp America, w77e58 Datasheet - Page 22
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w77e58
Manufacturer Part Number
w77e58
Description
8 Bit Microcontroller
Manufacturer
Winbond Electronics Corp America
Datasheet
1.W77E58.pdf
(85 pages)
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SM1_1: Serial port 1 Mode bit 1:
SM2_1:Multiple processors communication. Setting this bit to 1 enables the multiprocessor
REN_1:Receive enable: When set to 1 serial reception is enabled, otherwise reception is disabled.
TB8_1: This is the 9th bit to be transmitted in modes 2 and 3. This bit is set and cleared by software
RB8_1: In modes 2 and 3 this is the received 9th data bit. In mode 1, if SM2_1 = 0, RB8_1 is the stop
TI_1:
RI_1:
SERIAL DATA BUFFER 1
SBUF1.7-0: Serial data of the serial port 1 is read from or written to this location. It actually consists
ROMMAP
Bit:
communication feature in mode 2 and 3. In mode 2 or 3, if SM2_1 is set to 1, then RI_1 will
not be activated if the received 9th data bit (RB8_1) is 0. In mode 1, if SM2_1 = 1, then RI_1
will not be activated if a valid stop bit was not received. In mode 0, the SM2_1 bit controls the
serial port 1 clock. If set to 0, then the serial port 1 runs at a divide by 12 clock of the
oscillator. This gives compatibility with the standard 8052. When set to 1, the serial clock
become divide by 4 of the oscillator clock. This results in faster synchronous serial
communication.
as desired.
bit that was received. In mode 0 it has no function.
Transmit interrupt flag: This flag is set by hardware at the end of the 8th bit time in mode 0, or
at the beginning of the stop bit in all other modes during serial transmission. This bit must be
cleared by software.
Receive interrupt flag: This flag is set by hardware at the end of the 8th bit time in mode 0, or
halfway through the stop bits time in the other modes during serial reception. However the
restrictions of SM2_1 apply to this bit. This bit can be cleared only by software.
of two separate 8-bit registers. One is the receive resister, and the other is the transmit
buffer. Any read access gets data from the receive data buffer, while write accesses are
to the transmit data buffer.
SBUF1.7 SBUF1.6 SBUF1.5 SBUF1.4 SBUF1.3 SBUF1.2 SBUF1.1 SBUF1.0
Mnemonic: SBUF1
Mnemonic: ROMMAP
SM0_1 SM1_1 Mode
0
0
1
1
Bit:
7
0
1
0
1
WS
7
6
0
1
2
3
6
1
Description
Synchronous
Asynchronous
Asynchronous
Asynchronous
5
5
-
- 22 -
4
Length
4
-
8
10
11
11
3
Preliminary W77E58
3
-
Address: C1h
Address: C2h
Baud rate
4/12 Tclk
variable
64/32 Tclk
variable
2
2
-
1
1
-
0
0
-