saa-xc886clm Infineon Technologies Corporation, saa-xc886clm Datasheet - Page 44

• Manufacturer Part Number: saa-xc886clm
• Description: 8-bit Single Chip Microcontroller
• Manufacturer: Infineon Technologies Corporation

Table 10
Addr Register Name
CD H
CE H
CF H
RMAP = 0, PAGE 1
CA H
CB H
CC H
CD H
CE H
CF H
D2 H
D3 H
RMAP = 0, PAGE 2
CA H
CB H
CC H
CD H
CE H
CF H
D2 H
Data Sheet
ADC_LCBR
Limit Check Boundary Register
ADC_INPCR0
Input Class 0 Register
ADC_ETRCR
External Trigger Control
Register
ADC_CHCTR0
Channel Control Register 0
ADC_CHCTR1
Channel Control Register 1
ADC_CHCTR2
Channel Control Register 2
ADC_CHCTR3
Channel Control Register 3
ADC_CHCTR4
Channel Control Register 4
ADC_CHCTR5
Channel Control Register 5
ADC_CHCTR6
Channel Control Register 6
ADC_CHCTR7
Channel Control Register 7
ADC_RESR0L
Result Register 0 Low
ADC_RESR0H
Result Register 0 High
ADC_RESR1L
Result Register 1 Low
ADC_RESR1H
Result Register 1 High
ADC_RESR2L
Result Register 2 Low
ADC_RESR2H
Result Register 2 High
ADC_RESR3L
Result Register 3 Low
ADC Register Overview (cont’d)
Reset: B7 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Bit
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
SYNE
N1
rw
7
0
0
0
0
0
0
0
0
r
r
r
r
r
r
r
r
RESULT
RESULT
RESULT
RESULT
rh
rh
rh
rh
37
SYNE
N0
rw
6
BOUND1
rw
LCC
LCC
LCC
LCC
LCC
LCC
LCC
LCC
rw
rw
rw
rw
rw
rw
rw
rw
5
0
0
0
0
r
r
r
r
ETRSEL1
VF
VF
VF
VF
rw
rh
rh
rh
rh
4
RESULT
RESULT
RESULT
STC
rw
rh
rh
rh
Functional Description
DRC
DRC
DRC
DRC
rh
rh
rh
rh
3
0
0
0
0
0
0
0
0
SAA-XC886CLM
r
r
r
r
r
r
r
r
2
BOUND0
rw
ETRSEL0
V1.0, 2009-09
CHNR
CHNR
CHNR
CHNR
rw
rh
rh
rh
rh
1
RESRSEL
RESRSEL
RESRSEL
RESRSEL
RESRSEL
RESRSEL
RESRSEL
RESRSEL
rw
rw
rw
rw
rw
rw
rw
rw
0