SAA-XC886-6FFA AC Infineon Technologies, SAA-XC886-6FFA AC Datasheet
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... SAA-XC886CLM 8-Bit Single Chip Microcontroller Data Sheet V1.1 2010- ...
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... Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life ...
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... SAA-XC886CLM 8-Bit Single Chip Microcontroller Data Sheet V1.1 2010- ...
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... SAA-XC886 Data Sheet Revision History: V1.1 2010-08 Previous Versions: V1.0 2009-09 Page Subjects (major changes since last revision) 126 New parameter on weighted average temperature is added. 126 Maximum value of parameter V 126 Parameter We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document ...
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... Flash Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.2 Special Function Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2.2.1 Address Extension by Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2.2.2 Address Extension by Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.3 Bit Protection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2.3.1 Password Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2.4 SAA-XC886 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.2.4.1 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.2.4.2 MDU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2.4.3 CORDIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.2.4.4 System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.2.4.5 WDT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.2.4.6 Port Registers ...
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... Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.2.2 Supply Threshold Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.2.3 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 4.2.3.1 ADC Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 4.2.4 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 4.3 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.3.1 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.3.2 Output Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Data Sheet I-2 SAA-XC886CLM Table of Contents V1.1, 2010-08 ...
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... External Clock Drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 4.3.6 JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.3.7 SSC Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 5 Package and Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 5.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 5.2 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 5.3 Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Data Sheet I-3 SAA-XC886CLM Table of Contents V1.1, 2010-08 ...
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... Single Chip Microcontroller 1 Summary of Features The SAA-XC886 has the following features: • High-performance XC800 Core – compatible with standard 8051 processor – two clocks per machine cycle architecture (for memory access without wait state) – two data pointers • On-chip memory – ...
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... Synchronous serial channel (SSC) • On-chip debug support – 1 Kbyte of monitor ROM (part of the 12-Kbyte Boot ROM) – 64 bytes of monitor RAM • Package: – PG-TQFP-48 T • Temperature range A – SAA (-40 to 140 °C) Data Sheet : 2 SAA-XC886CLM Summary of Features V1.1, 2010-08 ...
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... The derivative itself, i.e. its function set, the temperature range, and the supply voltage • The package and the type of delivery For the available ordering codes for the SAA-XC886, please refer to your responsible sales representative or your local distributor. Data Sheet SAA-XC886CLM ...
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... General Device Information Chapter 2 contains the block diagram, pin configurations, definitions and functions of the SAA-XC886. 2.1 Block Diagram The block diagram of the SAA-XC886 is shown in SAA-XC886 12-Kbyte 1) Boot ROM 256-byte RAM + 64-byte monitor TMS RAM MBC RESET V DDP 1.5-Kbyte XRAM V SSP V DDC ...
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... Logic Symbol The logic symbols of the SAA-XC886 are shown in V AREF V AGND RESET MBC TMS XTAL1 XTAL2 Figure 3 SAA-XC886 Logic Symbol Data Sheet General Device Information Figure V V DDP SSP Port 0 7-Bit Port 1 8-Bit XC886 Port 2 8-Bit Port 3 8-Bit Port 4 3-Bit ...
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... P3.3 38 P3.4 39 P3.5 40 RESET SSP V 43 DDP MBC 44 P4.0 45 P4.1 46 P0 Figure 4 XC886 Pin Configuration, PG-TQFP-48 Package (top view) Data Sheet XC886 SAA-XC886CLM General Device Information 24 V AREF 23 V AGND 22 P2.6 21 P2.5 20 P2 SSP 17 V DDP V1.1, 2010-08 ...
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... Pin Definitions and Functions The functions and default states of the SAA-XC886 external pins are provided in Table 2. Table 2 Pin Definitions and Functions Symbol Pin Number P0 P0.0 11 P0.1 13 P0.2 12 P0.3 48 Data Sheet Type Reset Function State I/O Port 0 Port 8-bit bidirectional general purpose I/O port ...
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... CC62_1 TXD1_0 Hi-Z MRST_1 EXINT0_0 T2EX1_1 RXD1_0 COUT62_1 PU CLKOUT_1 Clock Output 8 SAA-XC886CLM General Device Information SSC Master Transmit Output/ Slave Receive Input Input/Output of Capture/Compare channel 2 UART1 Transmit Data Output/Clock Output SSC Master Receive Input/Slave Transmit Output External Interrupt Input 0 Timer 21 External Trigger Input ...
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... MRST_0 EXINT0_1 RXDC1_3 PU CCPOS0_1 EXINT5 T1_1 EXF2_0 RXDO_0 9 SAA-XC886CLM General Device Information UART Receive Data Input Timer 2 External Trigger Input MultiCAN Node 0 Receiver Input External Interrupt Input 3 Timer 0 Input JTAG Serial Data Output UART Transmit Data Output/Clock Output MultiCAN Node 0 Transmitter ...
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... PU CCPOS2_1 T13HR_0 T2_1 TXDC0_2 P1.5 and P1.6 can be used as a software chip select output for the SSC. 10 SAA-XC886CLM General Device Information CCU6 Hall Input 1 CCU6 Timer 12 Hardware Run Input External Interrupt Input 6 MultiCAN Node 0 Receiver Input Timer 21 Input CCU6 Hall Input 2 ...
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... AN2 Hi-Z AN3 Hi-Z AN4 Hi-Z AN5 Hi-Z AN6 Hi-Z AN7 11 SAA-XC886CLM General Device Information CCU6 Hall Input 0 External Interrupt Input 1 CCU6 Timer 12 Hardware Run Input JTAG Clock Input Input of Capture/Compare channel 1 Analog Input 0 CCU6 Hall Input 1 External Interrupt Input 2 CCU6 Timer 13 Hardware Run ...
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... COUT61_0 TXDC1_1 Hi-Z CC62_0 RXDC0_1 T2EX1_0 Hi-Z COUT62_0 EXF21_0 TXDC0_1 PD CTRAP_0 12 SAA-XC886CLM General Device Information CCU6 Hall Input 1 Input/Output of Capture/Compare channel 0 UART1 Transmit Data Output CCU6 Hall Input 0 Input/Output of Capture/Compare channel 1 Output of Capture/Compare channel 0 UART1 Transmit Data Output/Clock Output CCU6 Hall Input 2 ...
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... Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number P3.7 34 Data Sheet Type Reset Function State Hi-Z EXINT4 COUT63_0 13 SAA-XC886CLM General Device Information External Interrupt Input 4 Output of Capture/Compare channel 3 V1.1, 2010-08 ...
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... CCU6, Timer 0, Timer 1, Timer 21 and MultiCAN. Hi-Z RXDC0_3 CC60_1 Hi-Z TXDC0_3 COUT60_1 Hi-Z EXF21_1 COUT63_2 14 SAA-XC886CLM General Device Information MultiCAN Node 0 Receiver Input Output of Capture/Compare channel 0 MultiCAN Node 0 Transmitter Output Output of Capture/Compare channel 0 Timer 21 External Flag Output Output of Capture/Compare channel 3 ...
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... ADC Reference Ground I Hi-Z External Oscillator Input (backup for on-chip OSC, normally NC) O Hi-Z External Oscillator Output (backup for on-chip OSC, normally NC Test Mode Select I PU Reset Input I PU Monitor & BootStrap Loader Control 15 SAA-XC886CLM General Device Information V1.1, 2010-08 ...
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... The SAA-XC886 is based on a high-performance 8-bit Central Processing Unit (CPU) that is compatible with the standard 8051 processor. While the standard 8051 processor is designed around a 12-clock machine cycle, the SAA-XC886 CPU uses a 2-clock machine cycle. This allows fast access to ROM or RAM memories without wait state. ...
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... Memory Organization The SAA-XC886 CPU operates in the following five address spaces: • 12 Kbytes of Boot ROM program memory • 256 bytes of internal RAM data memory • 1.5 Kbytes of XRAM memory (XRAM can be read/written as program memory or external data memory) • A 128-byte Special Function Register area • ...
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... Memory Protection Strategy The SAA-XC886 memory protection strategy includes: • Read-out protection: The user is able to protect the contents in the Flash memory from being read – Flash protection is enabled by programming a valid password (8-bit non-zero value) via BSL mode 6. • Flash program and erase protection. ...
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... P-Flash and D-Flash contents, including the programmed password. The Flash protection is then disabled upon the next reset. Although no protection scheme can be considered infallible, the SAA-XC886 memory protection strategy provides a very high level of protection for a general purpose microcontroller. ...
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... As long as bit RMAP is set, the mapped SFR area can be accessed. This bit is not cleared automatically by hardware. Thus, before standard/mapped registers are accessed, bit RMAP must be cleared/set, respectively, by software. Data Sheet . To access SFRs in the mapped area, bit RMAP in SFR H 20 SAA-XC886CLM Functional Description bringing the number Figure 7 ...
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... SFR Data (to/from CPU) Figure 7 Address Extension by Mapping Data Sheet Standard Area ( Module 1 SFRs SYSCON0.RMAP Module 2 SFRs rw Module n SFRs Mapped Area (RMAP = 1) Module (n+1) SFRs Module (n+2) SFRs Module m SFRs 21 SAA-XC886CLM Functional Description Direct Internal Data Memory Address V1.1, 2010-08 ...
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... Address Extension by Paging Address extension is further performed at the module level by paging. With the address extension by mapping, the SAA-XC886 has a 256-SFR address range. However, this is still less than the total number of SFRs needed by the on-chip peripherals. To meet this requirement, some peripherals have a built-in local address extension mechanism for increasing the number of addressable SFRs ...
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... Save the contents of PAGE in STx before overwriting with the new value (this is done in the beginning of the interrupt routine to save the current page setting and program the new page number); or Data Sheet MOD_PAGE.PAGE rw Module 23 SAA-XC886CLM Functional Description PAGE 0 SFR0 SFR1 SFRx PAGE 1 SFR0 ...
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... The use of only write operations makes the system simpler and faster. Consequently, this mechanism significantly improves the performance of short interrupt routines. The SAA-XC886 supports local address extension for: • Parallel Ports • ...
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... PAGE are saved in STx before being overwritten with the new value the contents of PAGE are overwritten by the contents of STx. The value written to the bit positions of PAGE is ignored. 00 ST0 is selected. 01 ST1 is selected. 10 ST2 is selected. 11 ST3 is selected. 25 SAA-XC886CLM Functional Description Reset Value PAGE rw V1.1, 2010-08 H ...
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... Automatic restore page action. The value written to the bit positions PAGE is ignored and instead, PAGE is overwritten by the contents of the storage bit field STx indicated by STNR. r Reserved Returns 0 if read; should be written with 0. 26 SAA-XC886CLM Functional Description , writing 10011 to the the bit ...
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... The Bit Protection Scheme only recognizes three patterns. 11000 Enables writing of the bit field MODE. B 10011 Opens access to writing of all protected bits. B 10101 Closes access to writing of all protected bits B 27 SAA-XC886CLM Functional Description Reset Value PROTECT MODE and 00 , the bit field PASS ...
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... SAA-XC886 Register Overview The SFRs of the SAA-XC886 are organized into groups according to their functional units. The contents (bits) of the SFRs are summarized in Chapter 3.2.4.14. Note: The addresses of the bitaddressable SFRs appear in bold typeface. 3.2.4.1 CPU Registers The CPU SFRs can be accessed in both the standard and mapped memory areas (RMAP = ...
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... PCCIP PCCIP Type Bit Field PCCIP PCCIP PCCIP Type Bit Bit Field 0 Type r Bit Field IE IR RSEL Type Bit Field Type Bit Field Type 29 SAA-XC886CLM Functional Description TRAP_ ET1 EX1 ET0 PT1 PX1 PT0 PSH PT1H PX1H PT0H RS1 RS0 rwh ...
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... Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type 30 SAA-XC886CLM Functional Description DATA rw DATA rh DATA rw DATA rh DATA rw DATA rh DATA rw DATA rh DATA rw ...
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... Bit Field 0 CANS CANS RC2 RC1 Type r rwh rwh Bit Field 0 Type r Bit Field EXINT3 EXINT2 Type rw Bit Field 0 EXINT6 Type r Bit Field 0 NMI NMI ECC VDDP Type SAA-XC886CLM Functional Description DATAH rw DMAP INT_E EOC ERRO rwh rh ST_M ROTV MODE ODE IMOD ...
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... Type r Bit Field NDIV Type rw Bit Field VCO KDIV 0 SEL Type Bit Field PASS Type wh Bit Field Type Bit Field Type 32 SAA-XC886CLM Functional Description FNMI FNMI FNMI FNMI VDD OCDS FLASH PLL rwh rwh rwh rwh BRDIS BRPRE rw rw BR_VALUE rwh ...
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... Type rw r Bit Field 0 Type r Bit Field Type Bit Field 0 Type r Bit Bit Field 0 WINB EN Type r rw Bit Field Type Bit Field Type 33 SAA-XC886CLM Functional Description COUT COREL ADDRH rw CCU6 0 CANS SR1 RC4 rwh r rwh CCU6 0 CANS SR3 RC6 rwh r ...
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... P6 P5 Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type SAA-XC886CLM Functional Description WDT rh WDT PAGE ...
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... P6 P5 Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type SAA-XC886CLM Functional Description ...
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... Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Bit Field OP STNR Type w Bit Field ANON DW CTC Type rw rw Bit Field 0 Type r Bit Field ASEN ASEN Type SAA-XC886CLM Functional Description ...
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... Type rh r Bit Field Type Bit Field RESULT 0 Type rh r Bit Field Type Bit Field RESULT 0 Type rh r Bit Field Type Bit Field RESULT 0 Type SAA-XC886CLM Functional Description BOUND0 rw STC rw ETRSEL1 ETRSEL0 RESRSEL r 0 RESRSEL r 0 RESRSEL r 0 RESRSEL r 0 RESRSEL ...
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... Bit Field VFCT WFR 0 R Type Bit Field 0 Type r Bit Field CHINF CHINF CHINF Type Bit Field CHINC CHINC CHINC Type SAA-XC886CLM Functional Description RESULT rh VF DRC CHNR RESULT rh VF DRC CHNR RESULT rh VF DRC CHNR RESULT rh VF DRC CHNR rh rh ...
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... Bit Field CEV TREV FLUS H Type Bit Field Rsv 0 EMPT Y Type Bit Field EXTR ENSI RF Type Bit Field EXTR ENSI RF Type Bit Field EXTR ENSI RF Type SAA-XC886CLM Functional Description CHINS CHINS CHINS CHINS CHINP CHINP CHINP CHINP EVINF 0 EVINF EVINC 0 EVINC 4 1 ...
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... Bit Bit Field TF2 EXF2 Type rwh rwh Bit Field T2RE T2RH EDGE GS EN SEL Type Bit Field Type Bit Field Type Bit Field Type 40 SAA-XC886CLM Functional Description EXEN TR2 C/ rwh rw PREN T2PRE RC2 rwh RC2 rwh THL2 rwh THL2 rwh ...
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... STRH 0 P Type w r Bit Field RT12 RT12 RCC6 Type Bit Field RSTR RIDLE RWH E Type Bit Field 0 MCC6 3S Type r w Bit Field 0 MCC6 3R Type SAA-XC886CLM Functional Description THL2 rwh STNR 0 PAGE CC63SL rw CC63SH T12 T12R RES RES T13 T13R RES ...
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... Bit Field 0 DTR2 DTR1 Type Bit Field CTM CDIR STE1 2 Type Bit Field 0 STE1 3 Type r rh Bit Field Type 42 SAA-XC886CLM Functional Description CC60SL rwh CC60SH rwh CC61SL rwh CC61SH rwh CC62SL rwh CC62SH rwh CC63VL rh CC63VH rh T12PVL rwh T12PVH rwh T13PVL ...
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... Type Bit Field SSTR SIDLE SWHE Type Bit Field PSL63 0 Type rwh r Bit Field 0 SWSYN Type r rw Bit Field 0 T13TED Type SAA-XC886CLM Functional Description CC60VH rh CC61VL rh CC61VH rh CC62VL rh CC62VH rh MSEL60 rw MSEL62 rw ENCC ENCC ENCC ENCC ENCC 62R 61F 61R 60F rw rw ...
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... Bit Field ISTRP ISCC62 Type rw rw Bit Field IST12HR ISPOS2 Type rw rw Bit Field 0 Type r Bit Field Type Bit Field Type Bit Field Type Bit Field Type 44 SAA-XC886CLM Functional Description T13RSEL T12RSEL rw rw T12MODEN rw T13MODEN rw TRPM TRPM TRPM TRPEN rw MCMP rh CURH ...
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... Bit Bit Field SM0 SM1 SM2 Type Bit Field Type Bit Field 0 Type r Bit Field Type Bit Field 0 Type r Bit Field Type Bit Field Type 45 SAA-XC886CLM Functional Description CC62 CC61 POS1 POS0 CC62 COUT CC61 COUT PS 61PS PS 60PS rwh rwh rwh ...
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... Type Bit Field Type Bit Field Type Bit Field Type Bit Bit Field Type Bit Field CA9 CA8 CA7 Type rwh rwh rwh Bit Field 0 Type r 46 SAA-XC886CLM Functional Description CIS SIS AREN BEN PEN REN BSY rwh rwh rwh TB_VALUE ...
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... Bit Field SWBC HWB3C Type rw rw Bit Field DVEC DRET COMR Type rwh rwh rwh Bit Field Type Bit Field 0 Type r Bit Field Type Bit Field Type 47 SAA-XC886CLM Functional Description rwh CD rwh CD rwh CD rwh MBCO ALTDI MMEP MMOD N E rwh rw rwh rh ...
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... Table 17 OCDS Register Overview (cont’d) Addr Register Name EC H MMWR2 Reset Monitor Work Register 2 Data Sheet Bit Bit Field Type 48 SAA-XC886CLM Functional Description MMWR2 rw V1.1, 2010-08 0 ...
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... D-Flash and 64-byte for P-Flash 125 ns CCLK 2.6 ms SYS 102 ms SYS MHz ± 7.5% ( sys MHz ± 7.5% is the only frequency range for Flash sys is used for obtaining the worst case timing. 49 SAA-XC886CLM Functional Description MHz ± 7 the maximum CCLK V1.1, 2010-08 ...
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... A 3.3.1 Flash Bank Sectorization The SAA-XC886 product family offers Flash devices with either 24 Kbytes or 32 Kbytes of embedded Flash memory. Each Flash device consists of Program Flash (P-Flash) and Data Flash (D-Flash) bank(s) with different sectorization shown in types can be used for code and data storage. The label “Data” neither implies that the D-Flash is mapped to the data memory region, nor that it can only be used for data storage ...
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... However, if the parallel read feature is not desired due to certain timing constraints, it can be disabled by calling the parallel read disable subroutine. Data Sheet Functional Description Sector 9: 128-byte Sector 8: 128-byte Sector 7: 128-byte Sector 6: 128-byte Sector 5: 256-byte Sector 4: 256-byte Sector 3: 512-byte Sector 2: 512-byte Sector 1: 1-Kbyte Sector 0: 1-Kbyte D-Flash 51 SAA-XC886CLM V1.1, 2010-08 ...
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... Data Sheet 16 bytes 0000 ….. 0000 Program 1 H 1111 ….. 0000 Program 2 H Note: A Flash memory cell can be programmed from but not from 32-byte write buffers 52 SAA-XC886CLM Functional Description 16 bytes 1111 ….. 1111 H H 0000 ….. 0000 H H V1.1, 2010-08 ...
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... The XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt requests. In addition to the standard interrupt functions supported by the core, e.g., configurable interrupt priority and interrupt masking, the SAA-XC886 interrupt system provides extended interrupt support capabilities such as the mapping of each interrupt ...
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... TF0 TCON.5 ET0 IEN0.1 TF1 TCON.7 ET1 IEN0.3 RI SCON.0 >= IEN0.4 SCON.1 IE0 TCON.1 EX0 IT0 IEN0.0 TCON.0 IE1 TCON.3 EX1 IT1 IEN0.2 TCON.2 54 SAA-XC886CLM Functional Description Highest Lowest Priority Level 000B H IP.1/ IPH.1 P 001B H o IP.3/ l IPH 0023 H e IP.4/ IPH ...
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... Interrupt Request Sources (Part 2) Data Sheet TF2 >=1 EXF2 NDOV >=1 FDCON.2 ET2 >=1 IEN0.5 SYNEN CANSRC0 IRCON2.0 ADCSR0 IRCON1.3 ADCSR1 IRCON1.4 >=1 CANSRC1 EADC IRCON1.5 IEN1.0 CANSRC2 IRCON1.6 55 SAA-XC886CLM Functional Description Highest Lowest Priority Level 002B P H IP.5/ o IPH 0033 c H IP1.0/ e IPH1 ...
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... Data Sheet EIR IRCON1.0 >=1 TIR IRCON1.1 ESSC RIR IEN1.1 IRCON1.2 EXINT2 IRCON0.2 RI >=1 TI TF2 >=1 EX2 >=1 IEN1.2 NDOV UART1_FDCON.2 EOC CDSTATC.2 IRDY MDUSTAT.0 IERR MDUSTAT.1 56 SAA-XC886CLM Functional Description Highest Lowest Priority Level 003B H IP1.1/ IPH1 0043 H e IP1.2/ IPH1.2 EA IEN0 ...
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... EXINT6 EXICON1.4/5 MultiCAN_3 CANSRC3 IRCON2.4 Bit-addressable Request flag is cleared by hardware Figure 16 Interrupt Request Sources (Part 4) Data Sheet EXINT3 IRCON0.3 EXINT4 IRCON0.4 >=1 EXINT5 004B EXM IRCON0.5 IEN1.3 EXINT6 IRCON0.6 EA IEN0.7 57 SAA-XC886CLM Functional Description Highest Lowest Priority Level IP1.3/ e IPH1 V1.1, 2010-08 ...
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... Figure 17 Interrupt Request Sources (Part 5) Data Sheet >=1 0053 H ECCIP0 IP1.4/ IEN1.4 IPH1.4 >=1 005B H ECCIP1 IP1.5/ IEN1.5 IPH1.5 >=1 0063 H ECCIP2 IP1.6/ IEN1.6 IPH1.6 >=1 006B H ECCIP3 IEN1.7 IPH1.7 EA IEN0.7 58 SAA-XC886CLM Functional Description Highest Lowest Priority Level IP1.7/ V1.1, 2010-08 ...
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... This vector is accessed to service the corresponding interrupt node request. The interrupt service of each interrupt source can be individually enabled or disabled via an enable bit. The assignment of the SAA-XC886 interrupt sources to the interrupt vector address and the corresponding interrupt node enable bits are ...
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... XINTR9 004B H XINTR10 0053 H XINTR11 005B H XINTR12 0063 H XINTR13 006B H Data Sheet Assignment for SAA- XC886 MultiCAN Nodes 1 and 2 ADC[1:0] SSC External Interrupt 2 T21 CORDIC UART1 UART1 Fractional Divider (Normal Divider Overflow) MDU[1:0] External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 ...
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... Normal Divider Overflow, MDU, CORDIC Interrupt External Interrupt [6:3], MultiCAN Interrupt CCU6 Interrupt Node Pointer 0, MultiCAN interrupt 11 CCU6 Interrupt Node Pointer 1, MultiCAN Interrupt 12 CCU6 Interrupt Node Pointer 2, MultiCAN Interrupt 13 CCU6 Interrupt Node Pointer 3, MultiCAN Interrupt 14 Data Sheet Functional Description Table 20. Level (highest SAA-XC886CLM V1.1, 2010-08 ...
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... Parallel Ports The SAA-XC886 has 34 port pins organized into five parallel ports, Port 0 (P0) to Port 4 (P4). Each pin has a pair of internal pull-up and pull-down devices that can be individually enabled or disabled. Ports P0, P1, P3 and P4 are bidirectional and can be used as general purpose input/output (GPIO perform alternate input/output functions for the on-chip peripherals ...
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... Alternate Select Register 1 AltDataOut 3 AltDataOut 2 AltDataOut1 Px_Data Data Register AltDataIn Figure 18 General Structure of Bidirectional Port Data Sheet enable enable Out In Schmitt Trigger 63 SAA-XC886CLM Functional Description VDDP Pull enable Up Device Output Driver Input Driver Pull enable Down Device Pad V1.1, 2010-08 Pin ...
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... Figure 19 General Structure of Input Port Data Sheet Px_PUDSEL Pull-up/Pull-down Select Register Px_PUDEN Pull-up/Pull-down Enable Register Px_DIR Direction Register enable In Px_DATA Data Register Schmitt Trigger 64 SAA-XC886CLM Functional Description VDDP Pull enable Up Device Input Driver Pull enable Down Device Pad V1.1, 2010-08 Pin ...
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... V for the core, memory, on-chip oscillator, and peripherals Figure 20 shows the SAA-XC886 power supply system. A power supply of 5.0 V must be provided from the external power supply pin. The 2.5 V power supply for the logic is generated by the EVR. The EVR helps to reduce the power consumption of the whole chip and the complexity of the application board design ...
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... Reset Control The SAA-XC886 has five types of reset: power-on reset, hardware reset, watchdog timer reset, power-down wake-up reset, and brownout reset. When the SAA-XC886 is first powered up, the status of certain pins (see be defined to ensure proper start operation of the device. At the end of a reset sequence, the sampled values are latched to select the desired boot option, which cannot be modified until the next power-on reset or hardware reset ...
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... V DDP, DDC The second type of reset in SAA-XC886 is the hardware reset. This reset function can be used during normal operation or when the chip is in power-down mode. A reset input pin RESET is provided for the hardware reset. The Watchdog Timer (WDT) module is also capable of resetting the device if it detects a malfunction in the system ...
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... Disabled 3.7.2 Booting Scheme When the SAA-XC886 is reset, it must identify the type of configuration with which to start the different modes once the reset sequence is complete. Thus, boot configuration information that is required for activation of special modes and conditions needs to be applied by the external world through input pins. After power-on reset or hardware reset, the pins MBC, TMS and P0 ...
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... Power-down mode support The CGU consists of an oscillator circuit and a PLL. In the SAA-XC886, the oscillator can be from either of these two sources: the on-chip oscillator (9.6 MHz) or the external oscillator (4 MHz to 12 MHz). The term “oscillator” is used to refer to both on-chip oscillator and external oscillator, unless otherwise stated ...
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... In VCO bypass operation, the system clock is derived from the oscillator clock, divided by the P and K factors. Data Sheet osc fail detect lock detect PLL fvco fp core fn N:1 VCOBYP NDIV (Table 24) divided by the K factor. 1 × --- - SYS VCObase K 1 × ------------- × SYS OSC SAA-XC886CLM Functional Description OSCR LOCK fsys K:1 PLLBYP (3.1) (3.2) V1.1, 2010-08 ...
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... PLL mode. The PLL mode is used during normal system operation. System Frequency Selection For the SAA-XC886, the value fixed order to obtain the required fsys, the value of N and K can be selected by bits NDIV and KDIV respectively for different oscillator inputs. The output frequency must always be configured for 96 MHz. ...
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... Table 24 shows the VCO range for the SAA-XC886. Table 24 VCO Range f f VCOmin VCOmax 150 200 100 150 3.8.1 Recommended External Oscillator Circuits The oscillator circuit, a Pierce oscillator, is designed to work with both, an external crystal oscillator or an external stable clock source. It basically consists of an inverting amplifier and a feedback element with XTAL1 as input, and XTAL2 as output ...
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... Please refer to the minimum and maximum values of the negative resistance specified by the crystal supplier. Data Sheet f External Clock OSC Signal SAA-XC886CLM Functional Description f OSC XTAL1 XC886 Oscillator XTAL2 V SS Clock_EXOSC V1.1, 2010-08 ...
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... TLEN is set to 1). The resulting output frequency has a 50% duty cycle. XC886. fsys= 96MHz fosc OSC PLL N,P,K Figure 25 Clock Generation from Data Sheet Figure 25 shows the clock distribution of the SAA- CLKREL COREL TLEN Toggle f sys 74 SAA-XC886CLM ...
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... Power Saving Mode Action Idle Clock to the CPU is disabled. Slow-down Clocks to the CPU and all the peripherals are divided by a common programmable factor defined by bit field CMCON.CLKREL. Power-down Oscillator and PLL are switched off. Data Sheet MHz) sys 75 SAA-XC886CLM Functional Description V1.1, 2010-08 ...
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... Power Saving Modes The power saving modes of the SAA-XC886 provide flexible power consumption through a combination of techniques, including: • Stopping the CPU clock • Stopping the clocks of individual system components • Reducing clock speed of some peripheral components • Power-down of the entire system with fast restart capability ...
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... The WDT is reset at a regular interval that is predefined by the user. The CPU must service the WDT within this interval to prevent the WDT from causing an SAA-XC886 system reset. Hence, routine service of the WDT confirms that the system is functioning properly. This ensures that an accidental malfunction of the SAA-XC886 will be aborted in a user-specified time period ...
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... WDTREL with WDTWINB. For this feature to be useful, WDTWINB cannot be smaller than WDTREL. Data Sheet count, after which the system is reset H ( × ) × WDTIN – WDTREL P = --------------------------------------------------------------------------------------------------------- WDT f PCLK 28. This period can be calculated using the same formula by 78 SAA-XC886CLM Functional Description /128 PCLK PCLK × V1.1, 2010- (3.4) P WDT ...
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... Some numbers are rounded to 3 significant digits. Table 26 Watchdog Time Ranges Reload value Prescaler for In WDTREL 2 (WDTIN = 0) 24 MHz 21.3 μ 2. 5. Data Sheet Count No refresh Refresh allowed allowed f PCLK 79 SAA-XC886CLM Functional Description time 128 (WDTIN = 1) 24 MHz 1.37 ms 176 ms 350 ms V1.1, 2010-08 ...
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... Multiplication/Division Unit The Multiplication/Division Unit (MDU) provides fast 16-bit multiplication, 16-bit and 32-bit division as well as shift and normalize features. It has been integrated to support the SAA-XC886 Core in real-time control applications, which require fast mathematical computations. Features • Fast signed/unsigned 16-bit multiplication • ...
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... The result of a CORDIC calculation may return an approximation due to truncation of LSBs – Good accuracy of the CORDIC calculated result data, especially in circular mode • Interrupt – On completion of a calculation Data Sheet 15 15 ,(2 -1)] represents the range [-π,((2 81 SAA-XC886CLM Functional Description 15 15 -1)/2 )π] for solving 15 15 -1)/2 )π] V1.1, 2010-08 ...
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... Interrupt enabling and corresponding flag 3.13 UART and UART1 The SAA-XC886 provides two Universal Asynchronous Receiver/Transmitter (UART and UART1) modules for full-duplex asynchronous reception/transmission. Both are also receive-buffered, i.e., they can commence reception of a second byte before a previously received byte has been read from the receive register. However, if the first byte still has not been read by the time reception of the second byte is complete, one of the bytes will be lost ...
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... FDSTEP 1 FDEN&FDM 1 0 Adder f 00 DIV FDRES (overflow) MOD ‘0’ the fractional divider is disabled (FDEN = 0). For baud rate ) defined by bit field BRPRE in register BCON 83 SAA-XC886CLM Functional Description f 8-Bit Reload Value 8-Bit Baud Rate Timer R NDOV Section 3.14. V1.1, 2010-08 , PCLK ...
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... Data Sheet f BRPRE PCLK BRPRE × BR_VALUE + 1 f PCLK ------------------------------------------------------------------------------------ = BRPRE × × BR_VALUE Reload Value (BR_VALUE + ( 156 ( 156 ( 156 ( SAA-XC886CLM Functional Description × > BR_VALUE + 1 STEP × -------------- - 256 ) + 1 f /32. Hence, for a module PCLK Deviation Error ) V1.1, 2010-08 (3.5) (3.6) ...
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... 236 (EC H SMOD × PCLK Mode 1, 3 baud rate = ---------------------------------------------------- - × × 256 TH1 – , where n is defined by 256 - STEP. DIV 1 × ----------------------------- - MOD DIV 256 STEP – 85 SAA-XC886CLM Functional Description Deviation Error ) +0. +0. +0. +0. (3.7) Figure 29). Once the (3.8) V1.1, 2010-08 ...
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... Response time • Data bytes (according to UART protocol) • Checksum Header Protected Synch Figure 30 Structure of LIN Frame Data Sheet Figure 30. The frame consists of the: Frame slot Frame Response space Response Data 2 Data 1 identifier 86 SAA-XC886CLM Functional Description ), and ID field H Checksum Data N V1.1, 2010-08 ...
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... STEP 3: Synchronize the baud rate to the host STEP 4: Enter for Master Request Frame or for Slave Response Frame Note: Re-synchronization and setup of baud rate are always done for every Master Request Header or Slave Response Header LIN frame. Data Sheet Functional Description 87 SAA-XC886CLM V1.1, 2010-08 ...
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... Transmit). The clock signal is output via line MS_CLK (Master Serial Shift Clock) or input via line SS_CLK (Slave Serial Shift Clock). Both lines are normally connected to the pin SCLK. Transmission and reception of data are double-buffered. Figure 31 shows the block diagram of the SSC. Data Sheet Functional Description 88 SAA-XC886CLM V1.1, 2010-08 ...
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... Clock RIR TIR SSC Control Block Register CON EIR Status Control Pin 16-Bit Shift Control Register Receive Buffer Register RB Internal Bus 89 SAA-XC886CLM Functional Description SS_CLK MS_CLK Receive Int. Request Transmit Int. Request Error Int. Request TXD(Master) RXD(Slave) TXD(Slave) RXD(Master) V1.1, 2010-08 ...
Page 97
... Timer 0 operates as two 8-bit timers The timer registers, TL0 and TH0, operate as two separate 8-bit counters. Timer 1 is halted and retains its count even if enabled. Data Sheet Functional Description Table 31. In modes 0, 1 and 2, the two 90 SAA-XC886CLM V1.1, 2010-08 ...
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... Capture event triggered by falling/rising edge at pin T2EX • Captured timer value stored in register RC2 • Interrupt is generated with reload or capture event Data Sheet 32 timer, the timers count with an input clock of PCLK/12 , underflow at value defined in register overflow at FFFF SAA-XC886CLM Functional Description V1.1, 2010-08 ...
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... Fast emergency stop without CPU load via external signal (CTRAP) • Control modes for multi-channel AC-drives • Output levels can be selected and adapted to the power stage The block diagram of the CCU6 module is shown in Data Sheet Functional Description Figure 32. 92 SAA-XC886CLM V1.1, 2010-08 ...
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... T13 interrupt control Figure 32 CCU6 Block Diagram Data Sheet module kernel compare channel 0 1 dead- channel 1 time 1 control channel 2 1 channel 3 compare input / output control port control 93 SAA-XC886CLM Functional Description multi- trap channel control control CCU6_block_diagram V1.1, 2010-08 1 ...
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... Overview of the MultiCAN Features • Compliant to ISO 11898. Data Sheet MultiCAN Module Kernel Message CAN Object Node 1 Linked Buffer List Control CAN 32 Node 0 Objects CAN Control 94 SAA-XC886CLM Functional Description f ) and are CAN TXDC1 RXDC1 Port Control TXDC0 RXDC0 MultiCAN_XC8_overview V1.1, 2010-08 ...
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... Advanced Interrupt Handling: – interrupt output lines are available. Most interrupt requests can be individually routed to one of the 8 interrupt output lines. – Message postprocessing notifications can be flexibly aggregated into a dedicated register field of 64 notification bits. Data Sheet Functional Description 95 SAA-XC886CLM V1.1, 2010-08 ...
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... Analog-to-Digital Converter The SAA-XC886 includes a high-performance 10-bit Analog-to-Digital Converter (ADC) with eight multiplexed analog input channels. The ADC uses a successive approximation technique to convert the analog voltage levels from up to eight different sources. The analog input channels of the ADC are available at Port 2. ...
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... Condition MHz, where t ADCI Prescaling Ratio ÷ ÷ ÷ (default) ÷ may be reduced to 12 MHz, 6 MHz etc., ADC 97 SAA-XC886CLM Functional Description arbiter registers interrupts digital part analog components analog part 1 ADCI = f ADCI f frequency can be selected as ADCI Analog Clock 12 MHz (N.A) ...
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... Sample Phase f ADCI BUSY Bit SAMPLE Bit t SYN Figure 35 ADC Conversion Timing Data Sheet f becomes too low during slow-down mode. ADC t ) SYN ) Conversion Phase CONV 98 SAA-XC886CLM Functional Description Source Channel Result interrupt interrupt interrupt Write Result Phase t WR V1.1, 2010-08 ...
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... The dedicated MBC pin is used for external configuration and debugging control. Note: All the debug functionality described here can normally be used only after SAA- XC886 has been started in OCDS mode. 1) The pins of the JTAG port can be assigned to either the primary port (Port 0) or either of the secondary ports (Ports 1 and 2/Port 5) ...
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... This is a read-only register located inside the JTAG module, and is used to recognize the device(s) connected to the JTAG interface. Its content is shifted out when INSTRUCTION register contains the IDCODE command (opcode 04 also true immediately after reset. The JTAG ID register contents for the SAA-XC886 Flash devices are given in Table 34 JTAG ID Summary Device Type ...
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... Chip Identification Number The SAA-XC886 identity (ID) register is located at Page 1 of address B3 ID register However, for easy identification of product variants, the Chip H Identification Number, which is an unique number assigned to each product variant, is available. The differentiation is based on the product, variant type and device step information. Two methods are provided to read a device’ ...
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... Section 4.2 4.1.1 Parameter Interpretation The parameters listed in this section represent partly the characteristics of the SAA- XC886 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are indicated by the abbreviations in the “Symbol” column: • ...
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... Absolute Maximum Rating Maximum ratings are the extreme limits to which the SAA-XC886 can be subjected to without permanent damage. Table 36 Absolute Maximum Rating Parameters Parameter Ambient temperature Storage temperature Junction temperature Voltage on power supply pin with V respect to SS Voltage on any pin with respect ...
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... Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the SAA-XC886. All parameters mentioned in the following table refer to these operating conditions, unless otherwise noted. Table 37 Operating Condition Parameters Parameter Digital power supply voltage Digital ground voltage ...
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... DC Parameters The electrical characteristics of the DC Parameters are detailed in this section. 4.2.1 Input/Output Characteristics Table 38 provides the characteristics of the input/output pins of the SAA-XC886. Table 38 Input/Output Characteristics (Operating Conditions apply) Parameter Range DDP Output low voltage Output high voltage Input low voltage on port pins (all except P0.0 & ...
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... OZ1 I CC -10 10 ILX Σ – – 0 – Σ – 106 SAA-XC886CLM Electrical Parameters Unit Test Conditions V CMOS Mode V CMOS Mode 1) V CMOS Mode μA V IHP,min μA V ILP,max μA V ILP,max μA V IHP,min μA 0 < V < DDP ≤ 140°C ...
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... GPIO pin V when is powered off. DDP Data Sheet Symbol Limit Values min. max – 120 MVDDP I SR – 120 MVSS ) will flow if an overload current flows through an adjacent pin. TMS pin and INJ 107 SAA-XC886CLM Electrical Parameters Unit Test Conditions V1.1, 2010-08 ...
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... Supply Threshold Characteristics Table 39 provides the characteristics of the supply threshold in the SAA-XC886. 5.0V VDDP 2.5V VDDC V DDCPOR Figure 37 Supply Threshold Parameters Table 39 Supply Threshold Parameters (Operating Conditions apply) Parameters 1) V prewarning voltage DDC V brownout voltage in DDC 1) active mode RAM data retention voltage ...
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... CC – 1 – – 1 – CC – – 1 – – 1 – – 5 – – 1 109 SAA-XC886CLM Electrical Parameters Range) DDP Unit Test Conditions/ Remarks 1) V DDP 1) V AREF V AREF MHz module clock MHz internal analog clock See Figure 34 μs 1) μs 1) LSB 8-bit conversion ...
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... CC – 5.0 V. AGND DDP I ). The amount of error current depends on the overload The polarity of the injected error current is inverse OV 110 SAA-XC886CLM Electrical Parameters Range) DDP Unit Test Conditions/ Remarks 1) kΩ 1) kΩ into the adjacent pins. This error ...
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... R EXT V C AIN V Figure 38 ADC Input Circuits Data Sheet ANx EXT V AGNDx Reference Voltage Input Circuitry R V AREFx AREF V AGNDx 111 SAA-XC886CLM Electrical Parameters Analog Input Circuitry R AIN AINSW AREF AREFSW V1.1, 2010-08 ...
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... ADC Conversion Timing t t Conversion time ADC r = CTC + 2 for CTC = for CTC = CTC = Conversion Time Control (GLOBCTR.CTC), STC = Sample Time Control (INPCR0.STC (for 8-bit and 10-bit conversion respectively ADC ADC Data Sheet × × STC where , 112 SAA-XC886CLM Electrical Parameters V1.1, 2010-08 ...
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... DDP I 20.3 24.4 DDP I 13.7 17.0 DDP I 11.4 14.2 DDP = + 25 °C and RESET = load on ports. DDP , RESET = V B DDP 113 SAA-XC886CLM Electrical Parameters Unit Test Condition 5.0 V. DDP = + 140 °C and 5.5 V). A DDP load on ports. DDP , no load on ports. , RESET = V B V1.1, 2010-08 ...
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... Data Sheet Symbol Limit Values 1) typ PDP - V = 5.0 V. DDP V = 5.5 V. DDP = + 140 ° RXD/INT0 = V DDP AGND SS 114 SAA-XC886CLM Electrical Parameters range) DDP Unit Test Condition 2) max. μ ° μ ° rest of the ports are programmed to be DDP V1.1, 2010-08 3)4) 4)5) ...
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... V SS Figure 39 Rise/Fall Time Parameters V DDP V DDE V SS Figure 40 Testing Waveform, Output Delay + 0 Load V - 0.1 V Load Figure 41 Testing Waveform, Output High Impedance Data Sheet and Figure 41. 90 Test Points Timing Reference Points 115 SAA-XC886CLM Electrical Parameters 90% 10 DDE - 0 0 V1.1, 2010-08 ...
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... Output Rise/Fall Times Table 43 provides the characteristics of the output rise/fall times in the SAA-XC886. Table 43 Output Rise/Fall Times Parameters (Operating Conditions apply) Parameter Range DDP Rise/fall times 1) Rise/Fall time measurements are taken with 10% - 90% of pad supply. 2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. ...
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... Power-on Reset and PLL Timing Table 47 provides the characteristics of the power-on reset and PLL timing in the SAA- XC886. Table 44 Power-On Reset and PLL Timing (Operating Conditions apply) Parameter Pad operating voltage On-Chip Oscillator start-up time Flash initialization time RESET hold time ...
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... Power-on Reset Timing Data Sheet t OSCST PLL unlock t LOCK Reset Initialization 3) 2)ENPS control 3)As Programmed III) until Flash go II)until PLL is locked to Ready-to-Read 118 SAA-XC886CLM Electrical Parameters PLL lock Ready to Read t FINIT IV) CPU reset is released; Boot ROM software begin execution V1.1, 2010-08 ...
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... On-Chip Oscillator Characteristics Table 45 provides the characteristics of the on-chip oscillator in the SAA-XC886. Table 45 On-chip Oscillator Characteristics (Operating Conditions apply) Parameter Symbol f Nominal frequency NOM Δ f Long term frequency LT deviation Δ f Short term frequency ST deviation 1) Nominal condition 2.5 V, DDC Data Sheet Limit Values min ...
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... External Clock Drive XTAL1 Table 46 shows the parameters that define the external clock supply for SAA-XC886. These timing parameters are based on the direct XTAL1 drive of clock input signals. They are not applicable if an external crystal or ceramic resonator is considered. Table 46 External Clock Drive Characteristics (Operating Conditions apply) ...
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... JTAG Timing Table 47 provides the characteristics of the JTAG timing in the SAA-XC886. Table 47 TCK Clock Timing (Operating Conditions apply pF) Parameter TCK clock period TCK high time TCK low time TCK clock rise time TCK clock fall time 1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. ...
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... TDO valid output to high impedance from TCK 1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. TCK TMS TDI TDO Figure 46 JTAG Timing Data Sheet Symbol Limits min max 122 SAA-XC886CLM Electrical Parameters Unit Test Conditions V1.1, 2010-08 ...
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... SSC Master Mode Timing Table 49 provides the characteristics of the SSC timing in the SAA-XC886. Table 49 SSC Master Mode Timing (Operating Conditions apply pF) Parameter SCLK clock period MTSR delay from SCLK MRST setup to SCLK MRST hold from SCLK 1/f . When f SSCmin CPU CPU 2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation ...
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... Package and Quality Declaration Chapter 5 provides the information of the SAA-XC886 package and reliability section. 5.1 Package Parameters Table 50 provides the thermal characteristics of the package used in SAA-XC886. Table 50 Thermal Characteristics of the Packages Parameter PG-TQFP-48 Thermal resistance junction case Thermal resistance junction lead ...
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... Package Outline Figure 48 shows the package outlines of the SAA-XC886. 0.5 5.5 2) 0.22 ±0. Index Marking 1) Does not include plastic or metal protrusion of 0.25 max. per side 2) Does not include dambar protrusion of 0.08 max. per side Figure 48 PG-TQFP-48 Package Outline Data Sheet C 0 ...
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... Quality Declaration Table 51 shows the characteristics of the quality parameters in the SAA-XC886. Table 51 Quality Parameters Parameter Operation Lifetime when the device is used 1) at the four stated T A Operation Lifetime when the device is used the two stated A Weighted Average 3) Temperature ESD susceptibility ...
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... Published by Infineon Technologies AG ...