m37516e6hp Renesas Electronics Corporation., m37516e6hp Datasheet - Page 39

• Manufacturer Part Number: m37516e6hp
• Description: Single-chip 8-bit Cmos Microcomputer
• Manufacturer: Renesas Electronics Corporation.

7516 Group
Fig. 38 Structure of I
Table 12 Recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency
Note: Do not set an odd number to the START/STOP condition set bit (SSC4 to SSC0).
Fig. 39 Address data communication format
Rev.1.01
f(X
Oscillation
frequency
b 7
IN
) (MHz)
( 1 ) A m a s t e r - t r a n s m i t t e r t r a n s n m i t s d a t a t o a s l a v e - r e c e i v e r
( 2 ) A m a s t e r - r e c e i v e r r e c e i v e s d a t a f r o m a s l a v e - t r a n s m i t t e r
( 3 ) A m a s t e r - t r a n s m i t t e r t r a n s m i t s d a t a t o a s l a v e - r e c e i v e r w i t h a 1 0 - b i t a d d r e s s
( 4 ) A m a s t e r - r e c e i v e r r e c e i v e s d a t a f r o m a s l a v e - t r a n s m i t t e r w i t h a 1 0 - b i t a d d r e s s
S : S T A R T c o n d i t i o n
A : A C K b i t
S r : R e s t a r t c o n d i t i o n
8
8
4
2
S I S S I P
S
S
S
S
Slave address R/W
S l a v e a d d r e s s R / W
S l a v e a d d r e s s
1 s t 7 b i t s
S l a v e a d d r e s s
1 s t 7 b i t s
Jul 01, 2003
S S C 4 S S C 3 S S C 2 S S C 1 S S C 0
7 b i t s
7 b i t s
divide ratio
Main clock
7 b i t s
7 b i t s
2
8
2
2
2
C START/STOP condition control register
R / W
R / W
“0”
“ 1 ”
“ 0 ”
“ 0 ”
b 0
page 37 of 89
System
clock
(MHz)
P : S T O P c o n d i t i o n
R / W : R e a d / W r i t e b i t
4
1
2
1
( S 2 D : a d d r e s s 0 0 3 0
I
c o n t r o l r e g i s t e r
2
S T A R T / S T O P c o n d i t i o n s e t b i t
S C L / S D A i n t e r r u p t p i n p o l a r i t y
s e l e c t i o n b i t
S C L / S D A i n t e r r u p t p i n s e l e c t i o n b i t
R e s e r v e d
C S T A R T / S T O P c o n d i t i o n
A
A
A
A
0 : F a l l i n g e d g e a c t i v e
1 : R i s i n g e d g e a c t i v e
0 : S D A v a l i d
1 : S C L v a l i d
D o n o t w r i t e “ 1 ” t o t h i s b i t .
1 t o 8 b i t s
1 t o 8 b i t s
S l a v e a d d r e s s
2 n d b y t e s
S l a v e a d d r e s s
2 n d b y t e s
control register
START/STOP
D a t a
D a t a
XXX11010
XXX11000
XXX00100
XXX01100
XXX01010
XXX00100
condition
8 b i t s
8 b i t s
A
A
1 6
)
1 t o 8 b i t s
1 to 8 bits
A
A
D a t a
D a t a
1 t o 8 b i t s
6.75 s (27 cycles)
6.25 s (25 cycles)
S r
6.5 s (13 cycles)
5.5 s (11 cycles)
SCL release time
D a t a
5.0 s (5 cycles)
5.0 s (5 cycles)
: Master to slave
: Slave to master
A / A
A
Slave address
1st 7 bits
( s)
7 b i t s
A
P
P
1 t o 8 b i t s
Data
R / W
“ 1 ”
A / A
3.375 s (13.5 cycles)
3.125 s (12.5 cycles)
3.25 s (6.5 cycles)
2.75 s (5.5 cycles)
A
2.5 s (2.5 cycles)
2.5 s (2.5 cycles)
Setup time
1 t o 8 b i t s
P
D a t a
( s)
A
1 t o 8 b i t s
D a t a
3.375 s (13.5 cycles)
3.125 s (12.5 cycles)
3.25 s (6.5 cycles)
2.75 s (5.5 cycles)
2.5 s (2.5 cycles)
2.5 s (2.5 cycles)
A
Hold time
( s)
P