m37516e6hp Renesas Electronics Corporation., m37516e6hp Datasheet - Page 31
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m37516e6hp
Manufacturer Part Number
m37516e6hp
Description
Single-chip 8-bit Cmos Microcomputer
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.M37516E6HP.pdf
(92 pages)
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7516 Group
MULTI-MASTER I
The multi-master I
cuit, conforming to the Philips I
interface, offering both arbitration lost detection and a synchro-
n o u s f u n c t i o n s , i s u s e f u l f o r t h e m u l t i - m a s t e r s e r i a l
communications.
Figure 27 shows a block diagram of the multi-master I
terface and Table 7 lists the multi-master I
functions.
This multi-master I
register, the I
the I
condition control register and other control circuits.
When using the multi-master I
more to .
Note: Mitsubishi Electric Corporation assumes no responsibility for in-
Fig. 27 Block diagram of multi-master I
Rev.1.01
: Purchase of MITSUBISHI ELECTRIC CORPORATIONS I
an I
2
C control register, the I
fringement of any third-party’s rights or originating in the use of the
connection control function between the I
ports SCL
ter (002E
2
C system, provided that the system conforms to the I
Serial data
(S
S 2 D
DA
)
Serial
clock
(S
SIS
Jul 01, 2003
2
16
CL
1
C data shift register, the I
I
2
, SCL
).
C start/stop condition
)
SIP
2
C-BUS interface is a serial communications cir-
2
2
control register
C-BUS interface consists of the I
SSC4 SSC3 SSC2 SSC1 SSC0
, SDA
Noise
elimination
circuit
N o i s e
e l i m i n a t i o n
c i r c u i t
2
C-BUS INTERFACE
1
and SDA
page 29 of 89
2
C status register, the I
2
2
C-BUS data transfer format. This
C-BUS interface, set 1 MHz or
2
with the bit 6 of I
Clock
control
circuit
2
C clock control register,
2
2
C-BUS interface
C-BUS interface and the
D a t a
c o n t r o l
c i r c u i t
c i r c u i t
circuit
2
BB
A L
C-BUS interface
2
S0D
C control regis-
I
2
2
2
2
C c l o c k c o n t r o l r e g i s t e r
C start/stop
b7
2
C Standard Specification as defined by Philips.
2
C components conveys a license under the Philips I
S A D 6 S A D 5 SAD4 SAD3 SAD2 SAD1 S A D 0 R W B
S2
ACK A C K
C address
b 7
b 7
C-BUS in-
S
0
B I T
I
A d d r e s s c o m p a r a t o r
2
MODE
I
FAST
C data shift register
2
C address register
C C R 4 C C R 3 C C R 2 CCR1 CCR0
Clock division
Table 7 Multi-master I
SCL clock frequency
System clock
Communication mode
Format
Item
b0
b0
b0
System clock ( )
Internal data bus
= f(X
= f(X
IN
IN
MST TRX BB PIN
S1D I C control register
2
b7
S1
b 7
TISS
C-BUS interface functions
)/2 (high-speed mode)
)/8 (middle-speed mode)
In conformity with Philips I
standard:
In conformity with Philips I
standard:
16.1 kHz to 400 kHz (at
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
Master transmission
Master reception
Slave transmission
Slave reception
TSEL
2
2
C Patent Rights to use these components
Interrupt
generating
circuit
10BIT
SAD
I
2
A L S
C clock control register
E S 0
Function
A L A A S A D 0 LRB
I
2
C status register
I n t e r r u p t r e q u e s t s i g n a l
( I I C I R Q )
B C 2 B C 1 B C 0
S1D
Bit counter
= 4 MHz)
2
2
C-BUS
C-BUS
b 0
b0