mc56f8006 Freescale Semiconductor, Inc, mc56f8006 Datasheet - Page 78

• Manufacturer Part Number: mc56f8006
• Description: Digital Signal Controller
• Manufacturer: Freescale Semiconductor, Inc

Interrupt Vector Table
Appendix A
Interrupt Vector Table
Table 40
organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. As indicated, the priority of an
interrupt can be assigned to different levels, allowing some control over interrupt priorities. All level 3 interrupts are serviced
before level 2 and so on. For a selected priority level, the lowest vector number has the highest priority.
The location of the vector table is determined by the vector base address (VBA). Please see the MC56F8006 Peripheral
Reference Manual for detail.
By default, the chip reset address and COP reset address correspond to vector 0 and 1 of the interrupt vector table. In these
instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR
instructions.
78
Peripheral
ADCA
ADCB
CMP0
CMP1
CMP2
PWM
Core
Core
Core
Core
Core
Core
Core
Core
Core
Core
PMC
PLL
SCI
SCI
SPI
SPI
FM
I
2
C
provides the 56F8006/56F8002’s reset and interrupt priority structure, including on-chip peripherals. The table is
Number
Vector
10
11
12
13
14
15
16
17
18
19
20
21
22
23
2
3
4
5
6
7
9
9
Encoding
0x0A
0x0B
0x0C
0x0D
0x0E
User
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2
Table 40. Interrupt Vector Table Contents
Priority
Level
3
3
3
3
3
3
3
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Vector Base
Address +
P:0x0C
P:0x1C
P:0x2C
P:0x00
P:0x02
P:0x04
P:0x06
P:0x08
P:0x0A
P:0x0E
P:0x10
P:0x12
P:0x14
P:0x16
P:0x18
P:0x1A
P:0x1E
P:0x20
P:0x22
P:0x24
P:0x26
P:0x28
P:0x2A
P:0x2E
Phase-Locked Loop Loss of Locks and Loss of Clock
Reserved for COP Reset Overlay
Reload PWM and/or PWM Faults
SCI Receiver Full/Overrun/Errors
EOnCE Transmit Register Empty
Comparator 0 Rising/Falling Flag
Comparator 1 Rising/Falling Flag
Comparator 2 Rising/Falling Flag
Misaligned Long Word Access
EOnCE Receive Register Full
Flash Memory Access Status
Reserved for Reset Overlay
ADCB Conversion Complete
ADCA Conversion Complete
SCI Transmitter Empty/Idle
EOnCE Breakpoint Unit
SPI Transmitter Empty
EOnCE Step Counter
Low-Voltage Detector
EOnCE Trace Buffer
1
Interrupt Function
HW Stack Overflow
SPI Receiver Full
Illegal Instruction
I
2
C Interrupt
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