mc9s08gt16a Freescale Semiconductor, Inc, mc9s08gt16a Datasheet - Page 227

• Manufacturer Part Number: mc9s08gt16a
• Description: Hcs08 Microcontrollers 8-bit Microcontroller Family
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
1
2
3
Maximum ATD conversion clock frequency is 2 MHz. The max bus clock frequency is computed from the max ATD conversion
clock frequency times the indicated prescaler setting; i.e., for a PRS of 0, max bus clock = 2 (max ATD conversion clock
frequency) × 2 (Factor) = 4 MHz.
Use these settings if the maximum desired ATD conversion clock frequency is 1 MHz. The max bus clock frequency is
computed from the max ATD conversion clock frequency times the indicated prescaler setting; i.e., for a PRS of 0, max bus
clock = 1 (max ATD conversion clock frequency) × 2 (Factor) = 2 MHz.
Minimum ATD conversion clock frequency is 500 kHz. The min bus clock frequency is computed from the min ATD conversion
clock frequency times the indicated prescaler setting; i.e., for a PRS of 1, min bus clock = 0.5 (min ATD conversion clock
frequency) × 2 (Factor) = 1 MHz.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
PRS
RES8
1
2
1
1
1
0
0
0
The SGN bit is only effective when DJM = 0. When DJM = 1, SGN is ignored.
8-bit results are always in ATDRH.
Factor = (PRS +1) × 2
DJM
0
0
1
0
0
1
10
12
14
16
18
20
22
24
26
28
30
32
2
4
6
8
SGN
X
X
0
1
0
1
1
1
Table 14-3. Available Result Data Formats
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Table 14-4. Clock Prescaler Values
(2 MHz max ATD Clock)
10-bit : right justified : unsigned
10-bit : left justified : unsigned
8-bit : left justified
8-bit : left justified : unsigned
10-bit : left justified : signed
8-bit : left justified : signed
Data Formats of Result
Max Bus Clock
MHz
12
16
20
20
20
20
20
20
20
20
20
20
20
20
4
8
2
: unsigned
1
(1 MHz max ATD Clock)
Max Bus Clock
MHz
V
10
12
14
16
18
20
20
20
20
20
20
20
2
4
6
8
REFH
$FF:$C0
$7F:$C0
$FF:$00
$7F:$00
$FF:$00
$03:$FF
Analog-to-Digital Converter (S08ATDV3)
V
DDA
ATDRH:ATDRL
= V
Analog Input
DDA
2
, V
(500 kHz min ATD Clock)
REFL
$00:$00
$80:$00
$00:$00
$00:$00
$80:$00
$00:$00
V
Min Bus Clock
SSA
= V
SSA
MHz
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
3
227