mc9s08gt16a Freescale Semiconductor, Inc, mc9s08gt16a Datasheet - Page 226

• Manufacturer Part Number: mc9s08gt16a
• Description: Hcs08 Microcontrollers 8-bit Microcontroller Family
• Manufacturer: Freescale Semiconductor, Inc

Analog-to-Digital Converter (S08ATDV3)
226
Reset
ATDPU
RES8
ATDRH
ATDRH
Field
SGN
DJM
PRS
3:0
7
6
5
4
7
9
7
W
R
ATDPU
6
6
ATD Power Up — This bit provides program on/off control over the ATD, reducing power consumption when the
ATD is not being used. When cleared, the ATDPU bit aborts any conversion in progress.
0 Disable the ATD and enter a low-power state.
1 ATD functionality.
Data Justification Mode — This bit determines how the 10-bit conversion result data maps onto the ATD result
register bits. When RES8 is set, bit DJM has no effect and the 8-bit result is always located in ATDRH.
For left-justified mode, result data bits 9–2 map onto bits 7–0 of ATDRH, result data bits 1 and 0 map onto ATDRL
bits 7 and 6, where bit 7 of ATDRH is the most significant bit (MSB).
For right-justified mode, result data bits 9 and 8 map onto bits 1 and 0 of ATDRH, result data bits 7–0 map onto
ATDRL bits 7–0, where bit 1 of ATDRH is the most significant bit (MSB).
The effect of the DJM bit on the result is shown in
0 Result register data is left justified. See
1 Result register data is right justified. See
ATD Resolution Select — This bit determines the resolution of the ATD converter, 8-bits or 10-bits. The ATD
converter has the accuracy of a 10-bit converter. However, if 8-bit compatibility is required, selecting 8-bit
resolution will map result data bits 9-2 onto ATDRH bits 7-0.
The effect of the RES8 bit on the result is shown in
0 10-bit resolution selected.
1 8-bit resolution selected.
Signed Result Select — This bit determines whether the result will be signed or unsigned data. Signed data is
represented as 2’s complement data and is achieved by complementing the MSB of the result. Signed data mode
can be used only when the result is left justified (DJM = 0) and is not available for right-justified mode (DJM = 1).
When a signed result is selected, the range for conversions becomes –512 ($200) to 511 ($1FF) for 10-bit
resolution and –128 ($80) to 127 ($7F) for 8-bit resolution.
The effect of the SGN bit on the result is shown in
0 Left justified result data is unsigned.
1 Left justified result data is signed.
Prescaler Rate Select — This field of bits determines the prescaled factor for the ATD conversion clock.
Table 14-4
0
7
5
5
illustrates the divide-by operation and the appropriate range of bus clock frequencies.
4
4
DJM
0
6
3
3
RESULT
Figure 14-3. ATD Control Register (ATDC)
Table 14-2. ATDC Field Descriptions
MC9S08GT16A/GT8A Data Sheet, Rev. 1
2
2
Figure 14-5. Right-Justified Mode
RES8
Figure 14-4. Left-Justified Mode
0
5
1
1
9
0
0
Figure
SGN
Figure
0
4
Description
14-4.
Table
Table
ATDRL
ATDRL
14-5.
Table
7
7
14-3.
14-3.
14-3.
3
0
6
0
6
RESULT
5
5
0
4
4
2
PRS
3
3
Freescale Semiconductor
2
2
0
1
1
1
0
0
0
0
0