c8051t617 Silicon Laboratories, c8051t617 Datasheet - Page 101

• Manufacturer Part Number: c8051t617
• Description: Mixed Signal Byte-programmable Eprom Mcu
• Manufacturer: Silicon Laboratories

10.2. Power-Fail Reset/V
If the power supply monitor is enabled, when a power-down transition or power irregularity causes V
drop below V
(see Figure 10.2). When V
state. Note that even though internal data memory contents are not altered by the power-fail reset, it is
impossible to determine if V
‘1’, the data may no longer be valid. The V
state (enabled/disabled) is not altered by any other reset source. For example, if the V
abled and a software reset is performed, the V
Important Note: If the V
selected as a reset source. Selecting the V
may cause a system reset. The procedure for configuring the V
below:
See Figure 10.2 for V
See Table 10.2 for electrical characteristics of the V
SFR Definition 10.1. VDM0CN: V
Bit7:
Bit6:
Bits5–0: Reserved. Read = Variable. Write = don’t care.
VDMEN VDDSTAT Reserved Reserved Reserved Reserved Reserved Reserved
R/W
Bit7
Step 1. Enable the V
Step 2. Wait for the V
Step 3. Select the V
VDMEN: V
This bit is turns the V
resets until it is also selected as a reset source in register RSTSRC (SFR Definition 10.2).
The V
ing the V
reset. See Table 10.2 for the minimum V
0: V
1: V
V
This bit indicates the current power supply status (V
0: V
1: V
RST
DD
DD
DD
DD
DD
, the power supply monitor will drive the RST pin low and hold the CIP-51 in a reset state
STAT: V
Bit6
DD
R
Monitor Disabled.
Monitor Enabled.
is at or below the V
is above the V
DD
Monitor must be allowed to stabilize before it is selected as a reset source. Select-
DD
DD
monitor timing; note that the reset delay is not incurred after a V
DD
monitor as a reset source before it has stabilized may generate a system
DD
Monitor Enable.
DD
DD
Status.
DD
Bit5
DD
monitor has been disabled by software, it must be re-enabled before it is
R
DD
returns to a level above V
dropped below the level required for data retention. If the PORSF flag reads
monitor as a reset source (PORSF bit in RSTSRC = ‘1’).
DD
monitor (VDMEN bit in VDM0CN = ‘1’).
monitor to stabilize (see Table 10.1 for the VDD Monitor turn-on time).
DD
DD
Monitor
monitor circuit on/off. The V
monitor threshold.
DD
Bit4
R
DD
DD
monitor threshold.
DD
monitor is enabled after power-on resets; however its defined
Monitor Control
monitor as a reset source before it is enabled and stabilized
DD
Rev. 0.3
monitor will still be disabled after the reset.
DD
Bit3
R
DD
monitor.
C8051T610/1/2/3/4/5/6/7
Monitor turn-on time.
RST
, the CIP-51 will be released from the reset
Bit2
R
DD
DD
DD
Monitor output).
Monitor cannot generate system
monitor as a reset source is shown
Bit1
R
Bit0
R
DD
DD
monitor is dis-
monitor reset.
SFR Address
Reset Value
Variable
0xFF
DD
101
to