z8f083a ZiLOG Semiconductor, z8f083a Datasheet - Page 84

• Manufacturer Part Number: z8f083a
• Description: High-performance 8-bit Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS026308-1207
PWM DUAL OUTPUT Mode
In PWM DUAL OUTPUT mode, the timer outputs a PWM output signal pair (basic PWM
signal and its complement) through two GPIO port pins. The timer input is the system
clock. The timer first counts up to 16-bit PWM match value stored in the timer PWM high
and low byte registers. When the timer count value matches the PWM value, the timer
output toggles. The timer continues counting until it reaches the reload value stored in the
timer reload high and low byte registers. On reaching the reload value, the timer generates
an interrupt, the count value in the timer high and low byte registers is reset to
counting resumes.
If the TPOL bit in the timer control register is set to 1, the timer output signal begins as a
high (1) and transitions to low (0) when the timer value matches the PWM value. The
timer output signal returns to high (1) after the timer reaches the reload value and is reset
to
If the TPOL bit in the timer control register is set to 0, the timer output signal begins as a
low (0) and transitions to high (1) when the timer value matches the PWM value. The
timer output signal returns to low (0) after the timer reaches the reload value and is reset to
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The timer also generates a second PWM output signal: the timer output complement. The
timer output complement is the complement of the timer output PWM signal. A
programmable deadband delay is configured to time delay (0 to 128 system clock cycles)
PWM output transitions on these two pins from a low to a high (inactive to active). This
ensures a time gap between the deassertion of one PWM output to the assertion of its
complement.
The steps for configuring a timer for PWM DUAL OUTPUT mode and for initiating the
PWM operation are as follows:
1. Write to the timer control register to:
2. Write to the timer high and low byte registers to set the starting count value (typically
3. Write to the PWM high and low byte registers to set the PWM value.
4. Write to the PWM control register to set the PWM deadband delay value. The
0001H
–
–
–
–
0001H
PWM mode, counting always begins at the reset value of
deadband delay must be less than the duration of the positive phase of the PWM signal
(as defined by the PWM high and low byte registers). It must also be less than the
.
Disable the timer
Configure the timer for PWM DUAL OUTPUT mode. Setting the mode also
involves writing to TMODEHI bit in TxCTL1 register
Set the prescale value
Set the initial logic level (high or low) and PWM high/low transition for the timer
output alternate function
.
). This only affects the first pass in PWM mode. After the first timer reset in
Z8 Encore!
0001H
Product Specification
.
®
F083A Series
0001H
Timers
and
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