lh7a404n0e000b3 NXP Semiconductors, lh7a404n0e000b3 Datasheet - Page 47
lh7a404n0e000b3
Manufacturer Part Number
lh7a404n0e000b3
Description
Lh7a404 32-bit System-on-chip
Manufacturer
NXP Semiconductors
Datasheet
1.LH7A404N0E000B3.pdf
(75 pages)
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32-Bit System-on-Chip
Synchronous Memory Controller Waveforms
chronous Burst Read (page already open). Figure 19
shows the waveform and timing for synchronous mem-
ory to activate a bank and Write.
Preliminary data sheet
NOTES:
1. SDRAMcmd is the combination of nRAS, nCAS, nSDWE, and nSDCSx.
2. tOVXXX represents tOVRA, tOVCA, tOVSDW, or tOVSC.
3. tOHXXX represents tOHRA, tOHCA, tOHSDW, or tOHSC.
4. nDQM is static LOW.
5. SDCKE is static HIGH.
SDRAMcmd
SBANK[1:0]
Figure 18 shows the waveform and timing for a Syn-
SA[13:0],
D[31:0]
SCLK
SSPTXD/
SSPFRM
SSPRXD
SSPCLK
Figure 19. Synchronous Bank Activate and Write
tOVA
t OVXXX
Figure 18. Synchronous Burst Read
MSB
READ
COLUMN
BANK,
t OHXXX
t OVB
NXP Semiconductors
4 to 16 BITS
tISD tIHD
DATA n
DATA n + 1
LSB
DATA n + 2
DATA n + 3
LH7A404-24
LH7A404
LH7A404-13
47
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