lh79520 NXP Semiconductors, lh79520 Datasheet - Page 38

• Manufacturer Part Number: lh79520
• Description: Lh79520 System-on-chip
• Manufacturer: NXP Semiconductors

LH79520
External DMA Handshake Signal Timing
DREQ TIMING
DREQ1 must not transition from LOW to HIGH again
until after nDACK0 or DACK1 has been asserted.
DACK/DEOT TIMING
DACK1, DEOT0 and DEOT1 occur in relation to an
external bus access to/from the external peripheral that
requested the DMA transfer.
38
NOTE: tDREQ0L = DREQ0 LOW Pulse Width = 2 HCLK MIN.
As Figure 18 shows, once asserted, DREQ0 or
These timing diagrams indicate when nDACK0,
tDREQ1L = DREQ1 LOW Pulse Width = 2 HCLK MIN.
n DACK0
DREQ0,
DREQ1
DACK1
Figure 18. DREQ Timing Restrictions
CHANGE STATE
Rev. 01 — 16 July 2007
MUST NOT
NXP Semiconductors
DREQ
TRANSITON
DREQ MAY
read or the last word of a burst read from the requesting
peripheral. Figure 20 shows the timing with relation to
a single write or the last word of a burst write to the
requesting peripheral.
able when a Write to SDRAM occurs just prior to a sin-
gle word Write to the requesting peripheral. If the write
buffer is enabled for the SDRAM Controller, this can
cause the DACK/DEOT to occur an indeterminate
number of cycles prior to the actual Write to the
requesting peripheral.
Figure 19 shows the timing with relation to a single
The timing of DACK/DEOT may become unpredict-
tDREQ0L,
tDREQ1L
Preliminary data sheet
System-on-Chip
79520-158