lh75401 NXP Semiconductors, lh75401 Datasheet
lh75401
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lh75401 Summary of contents
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... The NXP BlueStreak LH75401/LH75411 family con- sists of two low-cost 16/32-bit System-on-Chip (SoC) devices. • LH75401 — contains the superset of features. • LH75411 — similar to LH75401, without CAN 2.0B. COMMON FEATURES • Highly Integrated System-on-Chip • ARM7TDMI-S™ Core • High Performance (84 MHz CPU Speed) – ...
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... LH75401/LH75411 ORDERING INFORMATION Type number Name LH75401N0Q100C0 LQFP144 LH75411N0Q100C0 LQFP144 2 NXP Semiconductors Table 1. Ordering information Package Description plastic low profile quad flat package; 144 leads; body 1.4 mm plastic low profile quad flat package; 144 leads; body 1.4 mm Rev. 01 — 16 July 2007 ...
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... CONTROLLER ADVANCED PERIPHERAL BUS BRIDGE COLOR LCD CONTROLLER ADVANCED LCD INTERFACE ADVANCED HIGH ADVANCED PERFORMANCE PERPHERAL BUS (AHB) Figure 1. LH75401 Block Diagram Rev. 01 — 16 July 2007 LH75401/LH75411 LH75401 REAL TIME CLOCK 76-BIT GENERAL PURPOSE I/O I/O CONFIGURATION SYNCHRONOUS SERIAL PORT TIMER (3) WATCHDOG TIMER CAN 2 ...
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... LH75401/LH75411 LH75411 BLOCK DIAGRAM ARM 7TDMI-S STATIC MEMORY CONTROLLER BROWNOUT DETECTOR LINEAR REGULATOR 4 NXP Semiconductors MHz 32.768 kHz OSCILLATOR, PLL, POWER MANAGEMENT, and RESET CONTROL INTERNAL 16KB SRAM AHB INTERFACE VECTORED INTERRUPT CONTROLLER TCM 16KB SRAM 4 CHANNEL DMA CONTROLLER ADVANCED ...
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... System-on-Chip PIN CONFIGURATION Figure 3. LH75401/LH75411 pin configuration Preliminary data sheet NXP Semiconductors 1 108 LH75401/ LH75411 36 73 002aad207 Rev. 01 — 16 July 2007 LH75401/LH75411 5 ...
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... PB0 nCS1 31 nCS0 32 PC7 A23 33 PC6 A22 34 VDD 35 PC5 A21 36 PC4 A20 37 PC3 A19 38 PC2 A18 6 NXP Semiconductors Table 2. LH75401 Numerical Pin List FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE I I Power None Ground None I I Power ...
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... System-on-Chip Table 2. LH75401 Numerical Pin List (Cont’d) PIN FUNCTION FUNCTION NO. AT RESET 2 39 PC1 A17 40 PC0 A16 41 VSS 42 VDD 43 A15 44 A14 45 A13 46 A12 47 A11 48 VSS 49 A10 VDD VSS nRESETIN ...
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... LH75401/LH75411 Table 2. LH75401 Numerical Pin List (Cont’d) PIN FUNCTION FUNCTION NO. AT RESET 2 81 nPOR 82 XTAL32IN 83 XTAL32OUT 84 VSSA_PLL 85 VDDA_PLL 86 XTALIN 87 XTALOUT 88 VSSA_ADC 89 AN3 (LR/Y-) PJ7 90 AN4 (Wiper) PJ6 91 AN9 PJ5 92 AN2 (LL/Y+) PJ4 93 AN8 PJ3 94 AN1 (UR/X-) PJ2 95 AN6 PJ1 96 AN0 (UL/X+) PJ0 97 VDDA_ADC 98 VDD ...
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... System-on-Chip Table 2. LH75401 Numerical Pin List (Cont’d) PIN FUNCTION FUNCTION NO. AT RESET 2 123 PG1 LCDCLS 124 PG0 LCDPS 125 PH7 LCDDCLK 126 VDD 127 VSS 128 PH6 LCDLP 129 PH5 LCDFP 130 PH4 LCDEN 131 PH3 LCDVD11 132 PH2 ...
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... DREQ Input 73 DACK Output 10 NXP Semiconductors Table 3. LH75401 Signal Descriptions DESCRIPTION MEMORY INTERFACE (MI) Static Memory Controller Write Enable Static Memory Controller Output Enable Static Memory Controller External Wait Control Static Memory Controller Byte Lane Strobe Static Memory Controller Byte Lane Strobe ...
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... System-on-Chip Table 3. LH75401 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE 120 LCDMOD Output 120 LCDVEEEN Output 121 LCDVDDEN Output 122 LCDDSPLEN Output 122 LCDREV Output 123 LCDCLS Output 124 LCDPS Output 125 LCDDCLK Output 128 LCDLP Output 128 LCDHRLP ...
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... LH75401/LH75411 Table 3. LH75401 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE 89 AN3 (LR/Y-) 90 AN4 (Wiper) 91 AN9 92 AN2 (LL/Y+) Input 93 AN8 94 AN1 (UR/X-) 95 AN6 96 AN0 (UL/X+) 117 116 115 CTCAP0[A:E] Input 114 113 117 CTCMP0[A:B] Output 116 118 CTCLK Input 111 CTCAP1[A:B] Input 110 111 CTCMP1[A:B] ...
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... System-on-Chip Table 3. LH75401 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE 72 PD6 73 PD5 74 PD4 76 PD3 Input/Output General Purpose I/O Signals - Port D 77 PD2 78 PD1 79 PD0 89 PJ7 90 PJ6 91 PJ5 92 PJ4 Input 93 PJ3 94 PJ2 95 PJ1 96 PJ0 99 PE7 100 PE6 101 PE5 102 PE4 ...
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... LH75401/LH75411 Table 3. LH75401 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE 73 INT5 Input 74 INT4 Input 76 INT3 Input 77 INT2 Input 78 INT1 Input 79 INT0 Input 81 nPOR Input 82 XTAL32IN Input 83 XTAL32OUT Output 86 XTALIN Input 87 XTALOUT Output 63 TEST2 Input 64 TEST1 Input 65 TMS Input 66 RTCK Output ...
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... Power None Ground None Rev. 01 — 16 July 2007 LH75401/LH75411 BUFFER BEHAVIOR DURING TYPE RESET Bidirectional Pull-up Bidirectional Pull-up Bidirectional Pull-up Bidirectional Pull-up Bidirectional Pull-up Bidirectional Pull-up Bidirectional Pull-up ...
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... LH75401/LH75411 Table 4. LH75411 Numerical Pin List (Cont’d) PIN FUNCTION FUNCTION NO. AT RESET 2 42 VDD 43 A15 44 A14 45 A13 46 A12 47 A11 48 VSS 49 A10 VDD VSS nRESETIN 63 TEST2 64 TEST1 65 TMS 66 RTCK 67 TCK 68 TDI ...
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... CTCMP0B 4 mA CTCMP0A Ground None LCDMOD LCDREV Rev. 01 — 16 July 2007 LH75401/LH75411 BUFFER BEHAVIOR DURING TYPE RESET Input Output Input Input Input Input Input Input Input Input Bidirectional Pull-up Bidirectional Pull-down ...
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... LH75401/LH75411 Table 4. LH75411 Numerical Pin List (Cont’d) PIN FUNCTION FUNCTION NO. AT RESET 2 126 VDD 127 VSS 128 PH6 LCDLP 129 PH5 LCDFP 130 PH4 LCDEN 131 PH3 LCDVD11 132 PH2 LCDVD10 133 PH1 LCDVD9 134 VDD 135 PH0 LCDVD8 136 ...
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... Static Memory Controller Chip Select Static Memory Controller Chip Select Static Memory Controller Chip Select Static Memory Controller Chip Select Address Signals DMA CONTROLLER (DMAC) DMA Request DMA Acknowledge Rev. 01 — 16 July 2007 LH75401/LH75411 NOTES ...
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... LH75401/LH75411 Table 5. LH75411 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE 120 LCDMOD Output 120 LCDVEEEN Output 121 LCDVDDEN Output 122 LCDDSPLEN Output 122 LCDREV Output 123 LCDCLS Output 124 LCDPS Output 125 LCDDCLK Output 128 LCDLP Output 128 LCDHRLP Output ...
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... Timer 0 Compare Outputs Common External Clock TIMER 1 Timer 1 Capture Inputs Timer 1 Compare Outputs Common External Clock TIMER 2 Timer 2 Capture Inputs Timer 2 Compare Outputs Common External Clock GENERAL PURPOSE INPUT/OUTPUT (GPIO) Rev. 01 — 16 July 2007 LH75401/LH75411 NOTES ...
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... LH75401/LH75411 Table 5. LH75411 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE 89 PJ7 90 PJ6 91 PJ5 92 PJ4 Input 93 PJ3 94 PJ2 95 PJ1 96 PJ0 99 PE7 100 PE6 101 PE5 102 PE4 Input/Output General Purpose I/O Signals - Port E 103 PE3 104 PE2 105 PE1 107 PE0 108 ...
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... POWER AND GROUND (GND) I/O Ring VDD I/O Ring VSS Core VDD supply (Output if Linear Regulator Enabled, Otherwise Input) Core VSS Linear Regulator Enable PLL Analog VSS PLL Analog VDD Supply A-to-D converter Analog VSS A-to-D converter Analog VDD Supply Rev. 01 — 16 July 2007 LH75401/LH75411 NOTES 2 23 ...
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... LH75401/LH75411 NETWORK SENSOR Figure 4. LH75401 System Application Example FUNCTIONAL OVERVIEW ARM7TDMI-S Processor The LH75401/LH75411 microcontrollers feature the ARM7TDMI-S core with an Advanced High-Performance Bus (AHB) 2.0 interface. The ARM7TDMI 16/32-bit embedded RISC processor and a member of the ARM7 Thumb family of processors. For more information, visit the ARM Web site at www ...
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... ARM7TDMI-S Core (Default) Preliminary data sheet NXP Semiconductors Memory Interface Architecture The LH75401/LH75411 microcontrollers provide the following data-path management resources on chip: • AHB and APB data buses • zero-wait-state TCM SRAM accessible via processor • internal SRAM accessible via processor, DMAC, and LCDC • ...
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... Advanced LCD Interface 0xFFFE5000 - 0xFFFE5FFF I/O Configuration Peripheral 0xFFFE6000 - 0xFFFEFFFF Reserved Static Random Access Memory Controller The LH75401/LH75411 microcontrollers have Static Random Access Memory (SRAM) organized into two 16 kB blocks: • TCM 0 Wait State SRAM is available to the processor as an ARM7TDMI-S bus slave. ...
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... The ALI also pro- vides a bypass mode that allows interfacing to the built- in timing ASIC in standard TFT and STN panels. NOTES: 1. The Advanced LCD Interface pertains to the LH75401 and LH75411 microcontrollers. 2. VGA and XGA modes require 66 MHz core speed. Universal Asynchronous ...
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... CAN protocol. Bus timing is critical to the CAN protocol. Therefore, the CAN Controller has two programmable Bus Timing Registers that define timing parameters. NOTE: The CAN Controller pertains to the LH75401 microcontrol- lers. Rev. 01 — 16 July 2007 System-on-Chip Preliminary data sheet ...
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... Four interrupts, each of which can be individually enabled or disabled using the SSP Control Register bits. A combined interrupt is also generated function of the individual interrupt requests. • Loopback Test Mode. Rev. 01 — 16 July 2007 LH75401/LH75411 29 ...
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... LH75401/LH75411 MODE For communications with Motorola SPI-compatible Motorola SPI devices. Clock polarity and phase are programmable. For communications with Texas Instruments DSP- SSI compatible Serial Synchronous Interface devices. National Semiconductor For communications with National Semiconductor Microwire Microwire-compatible devices. Watchdog Timer (WDT) ...
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... Synchronous Serial Port SSPRORINTR Synchronous Serial Port SSPRXTOINTR Synchronous Serial Port SSPINTR Synchronous Serial Port UART1 UARTRXINTR UART1 UART1 UARTTXINTR UART1 UART1 UARTINTR UART1 UART0 UARTINTR UART0 UART2 Interrupt UART2 DMA DMA CAN (LH75401) CAN Reserved (LH75411) Rev. 01 — 16 July 2007 LH75401/LH75411 SOURCE 31 ...
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... NOTE: TEST1, TEST2, and nRESETIN are latched on the rising edge of nPOR. The microcontroller stays in that operating mode until power is removed or nPOR transitions from LOW to HIGH. General Purpose Input/Output (GPIO) The LH75401/LH75411 microcontrollers have 10 GPIO ports: • Seven 8-bit ports • Two 7-bit ports • One 6-bit port. ...
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... LVCVD5 LVCVD4 LVCVD3 LVCVD2 LVCVD1 LVCVD0 NOTES: 1. MUSTN = Mono upper panel STN, dual and/or single panel. 2. MLSTN = Mono lower panel STN, dual panel only. Table 15. LCD External Pin Multiplexing (LH75401 and LH75411) DEFAULT EXTERNAL PIN MODE (NO LCD) PG4/LCDVEEEN/LCDMOD PG4 PG3/LCDVDDEN PG3 ...
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... LH75401/LH75411 ELECTRICAL SPECIFICATIONS Table 16. Absolute Maximum Ratings PARAMETER DC Core Supply Voltage (VDDC) DC I/O Supply Voltage (VDD) DC Analog Supply Voltage for ADC (VDDA0) DC Analog Supply Voltage for PLL (VDDA1) Storage Temperature (TSTG) NOTE: These ratings are only for transient conditions. Operation at or beyond absolute maximum rating conditions may affect reliability and cause permanent damage to the device ...
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... System-on-Chip. This change from crystal to oscillator will increase the robustness (i.e., noise immunity of the clock input to the SoC. Preliminary data sheet NXP Semiconductors Temp ( Celsius) ˚ Rev. 01 — 16 July 2007 LH75401/LH75411 2 V 1.95 V 1.9 V 1.85 V 1.8 V 1.75 V 1.7 V 1. LH754xx-106 35 ...
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... LH75401/LH75411 DC Characteristics All characteristics are specified over an operating temperature of −40°C to +85°C, and at minimum and maximum supply voltages. SYMBOL PARAMETER VIH CMOS Input HIGH Voltage VIL CMOS Input LOW Voltage VT+ Schmitt Trigger Positive Going Threshold VT- Schmitt Trigger Negative Going Threshold ...
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... VSSA VSSA (VREF+) -1.0 (VREF-) +1.0 VREF VDDA -60 0 VDDA 3.0 3.6 590 180 < 1 2.63 120 −40 Rev. 01 — 16 July 2007 LH75401/LH75411 UNITS NOTES 10 Bits CLK Cycles 1 CLK Cycles ns LSB LSB mV LSB µA 5 µ µA µA 4 µ ...
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... LH75401/LH75411 1024 1023 1022 1021 1020 1019 1018 9 8 CENTER OF A STEP OF THE ACTUAL 7 TRANSFER CURVE LSB OFFSET ERROR DNL 38 NXP Semiconductors IDEAL TRANSFER CURVE TRANSFER CURVE INTEGRAL NON-LINEARITY 1015 1016 1017 1018 1019 Figure 6. ADC Transfer Characteristics Rev. 01 — ...
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... ICHIP = Chip Current with Linear Regulator (Core + I/O) 2. ICORE, IIO, IANALOG are the respective current consumption specifications for VDDC, VDD, and VDDA. Table 23. Peripheral Current Consumption PERIPHERAL UARTs RTC DMA SSP Counter/Timers LCD Rev. 01 — 16 July 2007 LH75401/LH75411 PARAMETER TYP. UNITS ACTIVE MODE 50 ...
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... LH75401/LH75411 AC Characteristics All signal transitions are measured from the 50 % point of the signal. SIGNAL I/O LOAD PARAMETER D[15:0] Out 50 pF tOVD D[15:0] Out 50 pF tOHD D[15:0] In tIDD nCS3 - nCS0 Out 30 pF tOVCS nCS3 -nCS0 Out 30 pF tOHCS nOE Out 30 pF tOVOE nOE Out 30 pF tOHOE nBLE1 - nBLE0 Out 30 pF ...
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... States - 1) (where Wait States is from 2 to 31.) The signal tIDD is shown without a setup time, as measurements are made from the Address Valid point and HCLK is an internal signal, shown for reference only. Rev. 01 — 16 July 2007 LH75401/LH75411 LH754xx-100 41 ...
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... LH75401/LH75411 Figure 8. External Static Memory Write, One Wait State 42 NXP Semiconductors Rev. 01 — 16 July 2007 System-on-Chip Preliminary data sheet ...
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... System-on-Chip Figure 9. External Static Memory Write, Two Wait States Preliminary data sheet NXP Semiconductors Rev. 01 — 16 July 2007 LH75401/LH75411 43 ...
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... LH75401/LH75411 Figure 10. External Static Memory Read, One Wait State 44 NXP Semiconductors Rev. 01 — 16 July 2007 System-on-Chip Preliminary data sheet ...
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... System-on-Chip Figure 11. External Static Memory Read, nWAIT Active Preliminary data sheet NXP Semiconductors Rev. 01 — 16 July 2007 LH75401/LH75411 45 ...
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... LH75401/LH75411 Synchronous Serial Port Waveform Figure 12. Synchronous Serial Port Waveform 46 NXP Semiconductors Rev. 01 — 16 July 2007 System-on-Chip Preliminary data sheet ...
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... Figure 13 shows the timing for a peripheral-to-mem- ory data transfer, where Figure 13. Peripheral-to-Memory Data-Transfer Timing Preliminary data sheet NXP Semiconductors SoSize = DeSize and SoBurst = 4. • Figure 14 shows the timing for a memory-to-periph- eral data transfer, where SoSize = DeSize and SoBurst = 4. Rev. 01 — 16 July 2007 LH75401/LH75411 47 ...
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... LH75401/LH75411 Figure 14. Memory-to-Peripheral Data-Transfer Timing 48 NXP Semiconductors Rev. 01 — 16 July 2007 System-on-Chip Preliminary data sheet ...
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... TFT timing to accommodate these panels. AD-TFT/HR-TFT VERTICAL TIMING WAVEFORMS Figure 20 shows typical vertical timing waveforms for AD-TFT and HR-TFT panels. The power sequenc- ing and register information is the same as for TFT ver- tical timing. Rev. 01 — 16 July 2007 LH75401/LH75411 49 ...
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... LH75401/LH75411 Figure 15. STN Horizontal Timing Diagram 50 NXP Semiconductors Rev. 01 — 16 July 2007 System-on-Chip Preliminary data sheet ...
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... System-on-Chip Preliminary data sheet NXP Semiconductors Figure 16. STN Vertical Timing Diagram Rev. 01 — 16 July 2007 LH75401/LH75411 51 ...
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... LH75401/LH75411 52 NXP Semiconductors Figure 17. TFT Horizontal Timing Diagram Rev. 01 — 16 July 2007 System-on-Chip Preliminary data sheet ...
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... System-on-Chip Preliminary data sheet NXP Semiconductors Figure 18. TFT Vertical Timing Diagram Rev. 01 — 16 July 2007 LH75401/LH75411 53 ...
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... LH75401/LH75411 * CLCDCLK (INTERNAL) APBPeriphClkCtrl1:LCD AD-TFT and HR-TFT SIGNALS ARE TFT SIGNALS, RE-TIMED ClkPrescale:LCDPS (SHOWN FOR REFERENCE) LCDLP (HORIZONTAL SYNCHRONIZATION PULSE) LCDDCLK (PANEL CLOCK) Timing2:PCD Timing2:BCD Timing2:IPC Timing2:CPL LCDVD[11:0] LCDEN (DATA ENABLE) LCDDCLK (DELAYED FOR AD-TFT, HR-TFT) LCDVD[11:0] (DELAYED FOR AD-TFT, HR-TFT) ...
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... Preliminary data sheet NXP Semiconductors Figure 22 shows the suggested external compo- nents for the 14.7456 MHz crystal circuit to be used with the NXP LH75401/LH75411. The NAND gate rep- resents the logic inside the SoC. See the chart for crys- tal specifics. ENABLE ...
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... LH75401/LH75411 INTERNAL TO THE LH75400, LH75401, LH75410, LH75411 EXTERNAL TO THE LH75400, LH75401, LH75410, LH75411 NOTES parallel-resonant type crystal. (See table) 2. The nominal values for C1 and C2 shown are for a crystal specified load capacitance (CL). 3. The values for C1 and C2 are dependent upon the cystal's specified load capacitance and PCB stray capacitance ...
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... scale (1) ( 0.20 20.1 20.1 22.15 22.15 0.5 1 0.09 19.9 19.9 21.85 21.85 REFERENCES JEDEC JEITA MS-026 Package outline SOT486-1 (LQFP144) Rev. 01 — 16 July 2007 LH75401/LH75411 SOT486 detail X (1) (1) θ 0.75 1.4 1.4 7 0.2 0.08 0.08 o 0.45 1.1 1.1 0 EUROPEAN ...
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... LH75401/LH75411 144LQFP NOTE: Dimensions in mm. 58 NXP Semiconductors 21.2 0.5 17.5 Figure 24. Recommended PCB Footprint Rev. 01 — 16 July 2007 System-on-Chip 1.6 144LQFP Preliminary data sheet ...
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... Document ID Release date Data sheet status LH75401_411_N_1 20070716 Modifications: • First NXP version based on the LH75400/01/10/11 data sheet of 20070510 Preliminary data sheet NXP Semiconductors Table 27. Revision history Change notice Preliminary data sheet - Rev. 01 — 16 July 2007 LH75401/LH75411 Supersedes LH754xx Data Sheet 5-10-07 59 ...
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... LH75401/LH75411 1. Legal information 1.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. ...
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... Dear customer from June 1 , 2007 NXP Semiconductors has acquired the LH7xxx ARM Microcontrollers from Sharp Microelectronics. The following changes are applicable to the attached data sheet. In data sheets where the previous Sharp or Sharp Corporation references remain, please use the new links as shown below. ...
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... Terms and conditions of sale (DS) Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors ...
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... The product is not designed, authorized or warranted to be suitable for any other use, including medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage ...