p89c668hbbd NXP Semiconductors, p89c668hbbd Datasheet - Page 52

• Manufacturer Part Number: p89c668hbbd
• Description: 80c51 8-bit Flash Microcontroller Family
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Reduced EMI Mode
The AO bit (AUXR.0) in the AUXR register when set disables the
ALE output.
Reduced EMI Mode
AUXR (8EH)
AUXR.1
AUXR.0
Dual DPTR
The dual DPTR structure (see Figure 39) is a way by which the chip
will specify the address of an external data memory location. There
are two 16-bit DPTR registers that address the external memory,
and a single bit called DPS (AUXR1.0), that allows the program
code to switch between them.
AUXR1 (A2H)
Where:
The DPS bit status should be saved by software when switching
between DPTR0 and DPTR1.
The GF2 bit is a general purpose user-defined flag. Note that bit 2 is
not writable and is always read as a zero. This allows the DPS bit to
be quickly toggled simply by executing an INC AUXR1 instruction
without affecting the GF2 bit.
2002 Oct 28
New Register Name: AUXR1#
SFR Address: A2H
Reset Value: xxxxx0x0B
DPS (AUXR1.0), enables switching between DPTR0 and DPTR1.
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM
7
–
7
–
6
–
6
–
Select Reg
DPTR0
DPTR1
EXTRAM
AO
ENBOOT
5
–
5
4
–
4
–
(See more detailed description in
Figure 53.)
3
–
GF2
3
2
–
2
0
DPS
0
1
EXTRAM
1
1
–
DPS
AO
0
0
52
The ENBOOT bit determines whether the BOOTROM is enabled
or disabled. This bit will automatically be set if the status byte is
non zero during reset or PSEN is pulled low, ALE floats high, and
EA > V
cleared during reset.
DPTR Instructions
The instructions, that refer to DPTR, refer to the data pointer that is
currently selected by the DPS bit (AUXR1.0). The six instructions
that use the DPTR are as follows:
The data pointer can be accessed on a byte-by-byte basis by
specifying the low or high byte in an instruction which accesses the
SFRs. See application note AN458 for more details.
INC DPTR
MOV DPTR, #data16
MOV A, @ A+DPTR
MOVX A, @ DPTR
MOVX @ DPTR , A
JMP @ A + DPTR
AUXR1
DPS
BIT0
IH
on the falling edge of reset. Otherwise, this bit will be
P89C660/P89C662/P89C664/
(83H)
DPH
Increments the data pointer by 1
Loads the DPTR with a 16-bit constant
Move code byte relative to DPTR to ACC
Move external RAM (16-bit address) to
ACC
Move ACC to external RAM (16-bit
address)
Jump indirect relative to DPTR
Figure 39.
(82H)
DPL
DPTR1
DPTR0
P89C668
EXTERNAL
MEMORY
DATA
Product data
SU00745A