mb90f377pff-g Fujitsu Microelectronics, Inc., mb90f377pff-g Datasheet - Page 65
mb90f377pff-g
Manufacturer Part Number
mb90f377pff-g
Description
16-bit Proprietary Microcontroller
Manufacturer
Fujitsu Microelectronics, Inc.
Datasheet
1.MB90F377PFF-G.pdf
(140 pages)
- Current page: 65 of 140
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9. MI
(1) Register configuration of MI
Multi-address I
Multi-address I
Multi-address I
Multi-address I
Multi-address I
The Multi-address I
serial data line (SDA) and a serial clock line (SCL) . Among the devices connected with these two wires,
information is transmitted to one another. By recognizing the unique address of each device, it can operate as
a transmitting or receiving device in accordance with the function of each device. Among these devices, the
master/slave relation is established.
The Multi-address I
capacitance does not exceed 400 pF. It is a full-fledged multi-master bus equipped with collision detection and
communication adjustment procedures designed to avoid the destruction of data if two or more masters attempt
to start data transfer simultaneously. This macro provides 6 addresses to implement the multi-address function.
The communication adjustment procedure permits only one master to control the bus when two or more masters
attempt to control the bus so that messages are not lost or the contents of messages are not changed. Multi-
master means that multiple masters attempt to control the bus simultaneously without losing messages.
This Multi-address I
performs automatic Packet Error Code (PEC) generation and verification.
Address : 0000C0
Address : 0000C1
Address : 0000C2
Address : 0000C3
Address : 0000C4
2
C
Initial value
Initial value
Initial value
Initial value
Initial value
Read/write
Read/write
Read/write
Read/write
Read/write
2
2
2
2
2
C Bus Control Register (Lower)
C Bus Control Register (Upper)
C Bus Status Register (Lower)
C Bus Status Register (Upper)
C Data Register
H
H
H
H
H
2
2
C interface can connect two or more devices to the bus provided the upper limit of the bus
2
C (Inter IC Bus) interface is a simple structure bidirectional bus consisting of two wires : a
C interface includes MCU standby mode wake-up function, and a CRC-8 calculator that
BER
R/W
R/W
BB
D7
15
15
R
7
7
0
7
X
0
2
C
BEIE
RSC
R/W
R/W
D6
14
14
R
X
6
6
0
6
0
PMATCH
SCC
R/W
R/W
D5
AL
13
13
R
X
5
5
0
R
5
0
0
MSS
WUF
LRB
R/W
R/W
R/W
D4
12
12
R
X
4
0
4
0
0
4
RES
R/W
ACK
TRX
TDR
R/W
R/W
R/W
D3
11
11
R
X
3
0
0
3
0
0
3
PECE
GCAA
AAS
R/W
R/W
TCR
R/W
R/W
D2
MB90370/375 Series
10
10
R
2
0
2
0
2
X
0
0
INTE
GCA
MTR
LBT
R/W
R/W
R/W
R/W
D1
R
X
1
0
1
0
1
9
0
9
0
WUE
R/W
R/W
R/W
FBT
STR
R/W
INT
D0
R
X
0
0
0
0
0
8
0
8
0
Bit number
MBCRL
Bit number
MBCRH
Bit number
MBSRL
Bit number
MBSRH
Bit number
MDAR
(Continued)
65
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