lpc2364 NXP Semiconductors, lpc2364 Datasheet - Page 26

• Manufacturer Part Number: lpc2364
• Description: Single-chip 16-bit/32-bit Microcontrollers; Up To 512 Kb Flash With Isp/iap, Ethernet, Usb 2.0, Can, And 10-bit Adc/dac
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2364_66_68_3
Product data sheet
7.20.1 Features
7.20 General purpose 32-bit timers/external event counters
7.21 Pulse width modulator
The LPC2364/66/68 include four 32-bit Timer/Counters. The Timer/Counter is designed to
count cycles of the system derived clock or an externally-supplied clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. The Timer/Counter also includes two capture inputs to trap the timer
value when an input signal transitions, optionally generating an interrupt.
The PWM is based on the standard Timer block and inherits all of its features, although
only the PWM function is pinned out on the LPC2364/66/68. The Timer is designed to
count cycles of the system derived clock and optionally switch pins, generate interrupts or
perform other actions when specified timer values occur, based on seven match registers.
The PWM function is in addition to these features, and is based on match register events.
The ability to separately control rising and falling edge locations allows the PWM to be
used for more applications. For instance, multi-phase motor control typically requires three
non-overlapping PWM outputs with individual control of all three pulse widths and
positions.
Two match registers can be used to provide a single edge controlled PWM output. One
match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon
match. The other match register controls the PWM edge position. Additional single edge
controlled PWM outputs require only one match register each, since the repetition rate is
the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a
rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs.
Three match registers can be used to provide a PWM output with both edges controlled.
Again, the PWMMR0 match register controls the PWM cycle rate. The other match
registers control the two PWM edge positions. Additional double edge controlled PWM
outputs require only two match registers each, since the repetition rate is the same for all
PWM outputs.
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A 32-bit Timer/Counter with a programmable 32-bit prescaler.
Counter or Timer operation.
Two 32-bit capture channels per timer, that can take a snapshot of the timer value
when an input signal transitions. A capture event may also generate an interrupt.
Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
Rev. 03 — 20 December 2007
LPC2364/66/68
Fast communication chip
© NXP B.V. 2007. All rights reserved.
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