lpc2294hbd144-01 NXP Semiconductors, lpc2294hbd144-01 Datasheet - Page 46

• Manufacturer Part Number: lpc2294hbd144-01
• Description: 16/32-bit Arm Microcontrollers 256 Kb Isp/iap Flash With Can, 10-bit Adc And External Memory Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 12.
C
[1]
[2]
[3]
[4]
[5]
Table 13.
[1]
LPC2292_2294_6
Product data sheet
Symbol
t
t
t
t
t
t
t
Access cycle
standard read
standard write
burst read - initial
burst read - subsequent 3
BLSHDNV
CHDV
CHWEL
CHBLSL
CHWEH
CHBLSH
CHDNV
L
= 25 pF, T
Except on initial access, in which case the address is set up T
T
Latest of address valid, CS LOW, OE LOW to data valid.
Address valid to data valid.
Earliest of CS HIGH, OE HIGH, address change to data invalid.
See the LPC2119/2129/2194/2292/2294 User Manual for a description of the WSTn bits.
cy(CCLK)
External memory interface dynamic characteristics
Parameter
BLS HIGH to data invalid
time
XCLK HIGH to data valid
time
XCLK HIGH to WE LOW
time
XCLK HIGH to BLS LOW
time
XCLK HIGH to WE HIGH
time
XCLK HIGH to BLS HIGH
time
XCLK HIGH to data invalid
time
Standard read access specifications
=
amb
1
CCLK
= 40 C
.
Max frequency
f
f
f
f
MAX
MAX
MAX
MAX
--------------------------------
t
--------------------------------- -
t
------------------------------- -
t
-------------------------------- -
t
RAM
WRITE
INIT
ROM
2
2
1
Conditions
+
+
+
WST 1
WST 1
+
+
WST 2
+
1
20 ns
20 ns
+
20 ns
Rev. 06 — 10 December 2007
5 ns
16/32-bit ARM microcontrollers with external memory interface
WST 1
WST
WST
integer
N/A
WST 1
WST 2
cy(CCLK)
[2]
[1]
0; round up to
setting
Min
(2
-
-
-
-
-
-
t
------------------------------- - 2
t
-------------------------------- 2
t
------------------------------------------- -
INIT
RAM
WRITE
t
t
cy CCLK
earlier.
cy CCLK
…continued
T
t
cy CCLK
+
cy(CCLK)
+
20 ns
20 ns
–
t
CYC
–
)
–
+
5
5
LPC2292/LPC2294
Memory access time requirement
t
t
t
t
INIT
RAM
WRITE
ROM
t
t
t
cy CCLK
cy CCLK
cy CCLK
Typ Max
-
-
-
-
-
-
-
t
cy CCLK
(2
10
10
10
10
10
10
–
T
20 ns
© NXP B.V. 2007. All rights reserved.
2
2
cy(CCLK)
+
+
1
WST 1
WST 1
+
WST 2
) + 5 ns
–
–
20 ns
46 of 54
20 ns
–
Unit
ns
ns
ns
ns
ns
ns
5 ns