p87c770aar NXP Semiconductors, p87c770aar Datasheet - Page 12

• Manufacturer Part Number: p87c770aar
• Description: Microcontrollers Ntsc With On-screen Display Closed Caption
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9
In order to reduce power consumption three reduced
power modes are available: Standby, Idle and
Power-down.
9.1
In Standby mode full CPU functionality is available but all
analog functions (including the OSD) are disabled.
Power-on reset and the oscillator remain active.
The following also remain active during Standby mode.
The Standby mode is entered by setting the STBY bit in
the STBCON register to a logic 1. Recovering from the
Standby mode is achieved by setting the STBY bit back to
a logic 0. After entering the normal mode a waiting time of
10 s has to be taken into account in order to allow the
analog circuitry to stabilize.
9.2
Idle mode operation permits all functions to continue to
work with the exception that the CPU clock is halted.
The following functions remain active during Idle mode:
9.2.1
The instruction that sets the IDL bit in the PCON register is
the last instruction executed before entering Idle mode.
Once in the Idle mode the system oscillator keeps running
but the internal clock is gated away from the CPU, but not
gated away from the interrupts, timers and serial port
functions. The CPU status is preserved along with the
Stack Pointer, Program Counter, Program Status Word
and Accumulator. The RAM and all other registers
maintain their data during Idle mode. The port pins retain
the logical states they were holding at Idle mode activation.
9.2.2
There are two methods used to terminate the Idle mode.
Assertion of any enabled interrupt will cause the IDL bit to
be cleared by hardware, thus terminating the Idle mode.
The interrupt is serviced, and following the instruction
1999 Jun 11
CPU
External interrupts INT0 and INT1
T0, T1 and T3
I
PWM outputs.
T0, T1 and T3 (Watchdog Timer)
I
External interrupts.
Microcontrollers for NTSC TVs with On-Screen
Display (OSD) and Closed Caption (CC)
2
2
C-bus interface
C-bus
REDUCED POWER MODES
Standby mode
Idle mode
E
R
NTERING
ECOVERING FROM
I
DLE MODE
I
DLE MODE
12
RETI, the next instruction to be executed will be the one
following the instruction that put the device into the Idle
mode.
Flag bits GF0 and GF1 may be used to determine whether
the interrupt was received during normal execution or
during Idle mode. For example, the instruction that writes
to the IDL bit can also set or clear one or both flag bits.
When Idle mode is terminated by an interrupt, the service
routine can examine the status of the flag bits.
The second method of terminating the Idle mode is with an
external hardware reset. Since the oscillator is still
running, the hardware reset is required to be active for only
two machine cycles to complete the reset operation. Reset
redefines all SFRs, but does not affect the on-chip RAM.
9.3
The Power-down operation freezes the oscillator and all
on-chip operations stop. The Power-down mode can only
be entered if the EW bit in SFR BWC is LOW; then the
Power-down mode is entered by setting the PD bit in the
PCON register to a logic 1.
The instruction which sets the PD bit in PCON is the last
instruction executed prior to going into the Power-down
mode. The contents of the on-chip RAM and SFRs are
preserved. The port pins output the values held by their
respective SFRs.
In the Power-down mode V
power consumption. However, the supply voltage must not
be reduced until Power-down mode is active, and must be
restored before the hardware reset is applied and frees the
oscillator. An on-chip delay counter will count 2048 system
oscillator cycles before enabling the internal clock.
9.3.1
If either of the external interrupts INT0 and INT1 is
switched to level-sensitive and enabled then the interrupt
can be used to wake-up the P8xCx70 from the
Power-down mode. To ensure that the oscillator is stable
before the controller restarts, the internal clock will remain
inactive for 2048 system oscillator cycles.
9.3.2
The Power-down mode can be terminated by holding the
RESET pin HIGH for two machine cycles, this clears the
PD bit. The on-chip delay counter will count 2048 system
oscillator cycles before enabling the internal clock.
Power-down mode
W
INTERRUPTS
W
AKE
AKE
-
-
UP FROM
UP FROM
P
P
OWER
OWER
DD
may be reduced to minimize
P8xCx70 family
-
-
DOWN USING EXTERNAL
DOWN USING
Product specification
RESET