p87lpc778-01 NXP Semiconductors, p87lpc778-01 Datasheet - Page 32

• Manufacturer Part Number: p87lpc778-01
• Description: P87lpc778 Cmos Single-chip 8-bit 80c51 Microcontroller With 128-byte Data Ram, 8 Kb Otp
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 12378
Product data
8.8 Interrupts
Table 29:
Table 30:
The P87LPC778 uses a four priority level interrupt structure. This allows great
flexibility in controlling the handling of the P87LPC778’s many interrupt sources. The
P87LPC778 supports up to 13 interrupt sources.
Each interrupt source can be individually enabled or disabled by setting or clearing a
bit in registers IEN0 or IEN1. The IEN0 register also contains a global disable bit, EA,
which disables all interrupts at once.
Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the IP0, IP0H, IP1, and IP1H registers. An interrupt service
routine in progress can be interrupted by a higher priority interrupt, but not by another
interrupt of the same or lower priority. The highest priority interrupt service cannot be
interrupted by any other interrupt source. So, if two requests of different priority levels
are received simultaneously, the request of higher priority level is serviced.
If requests of the same priority level are received simultaneously, an internal polling
sequence determines which request is serviced. This is called the arbitration ranking.
Note that the arbitration ranking is only used to resolve simultaneous requests of the
same priority level.
SLAVEN,
MASTRQ,
MASTER
All 0
All 0
Any or all 1
Any or all 1
CT1, CT0
1 0
0 1
0 0
1 1
Interaction of TIRUN with SLAVEN, MASTRQ, and MASTER
CT1, CT0 values
TIRUN
0
1
0
1
Min Time Count
(Machine Cycles)
7
6
5
4
Rev. 01 — 31 March 2004
OPERATING MODE
The I
does not run. This is the state assumed after a reset. If
an I
certain times, it should write SLAVEN, MASTRQ, and
TIRUN all to zero.
The I
The I
of Timer I run for min-time generation, but the hi-order
bits do not, so that there is no checking for I
being ‘hung.’ This configuration can be used for very
slow I
The I
frames on the I
SCL, and by Start and Stop conditions. This is the
normal state for I
2
C-bus application wants to ignore the I
2
2
2
2
2
C-bus interface is disabled. Timer I is cleared and
C-bus interface is disabled.
C-bus interface is enabled. The 3 low-order bits
C-bus interface is enabled. Timer I runs during
CPU Clock Max
(for 100 kHz I
8.4 MHz
7.2 MHz
6.0 MHz
4.8 MHz
C-bus operation.
CMOS single-chip 8-bit microcontroller
2
C-bus, and is cleared by transitions on
2
C-bus operation.
2
C-bus)
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
P87LPC778
Timeout Period
(Machine Cycles)
1023
1022
1021
1020
2
2
C-bus at
C-bus
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