p80c550efaa NXP Semiconductors, p80c550efaa Datasheet - Page 8

• Manufacturer Part Number: p80c550efaa
• Description: 80c51 8-bit Microcontroller Family 4k/128 Otp/rom/romless, Channel Watchdog Timer
• Manufacturer: NXP Semiconductors

Philips Semiconductors
A/D CONVERTER
The analog input circuitry consists of an 8-input analog multiplexer
and an analog-to-digital converter with 8-bit resolution. In the LCC
package, the analog reference voltage and analog power supplies
are connected via separate input pins; in the DIP package, Vref+ is
combined with AV
inputs are alternate functions to port 1, which is an input only port.
Digital input to port 1 can be read any time during an A/D
conversion. Care should be exercised in mixing analog and digital
signals on port 1, because cross talk from the digital input signals
can degrade the A/D conversion accuracy of the analog input. An
A/D conversion requires 40 machine cycles.
The A/D converter is controlled by the ADCON special function
register. The input channel to be converted is selected by the analog
multiplexer by setting ADCON register bits, ADDR2–ADDR0 (see
Figure 2). These bits can only be changed when ADCI and ADCS
are both low.
The completion of the 8-bit ADC conversion is flagged by ADCI in
the ADCON register and the result is stored in the special function
register ADAT.
An ADC conversion in progress is unaffected by a software ADC
start. The result of a completed conversion remains unaffected
provided ADCI remains at a logic 1. While ADCS is a logic 1 or
ADCI is a logic 1, a new ADC START will be blocked and
consequently lost. An A/D conversion in progress will be aborted
when the idle or power-down mode is entered. The result of a
completed conversion (ADCI = logic 1) remains unaffected when
entering the idle mode, but will be lost if power-down mode is
entered. See Figure 3 for the A/D input equivalent circuit.
The analog input pins ADC0-ADC7 may still be used as digital
inputs. The analog input channel that is selected by the
ADDR2-ADDR0 bits in ADCON cannot be used as a digital input.
Reading the selected A/D channel as a digital input will always
return a 1. The unselected A/D inputs may always be used as digital
inputs.
On RESET the A/D port pins are set to the Digital mode and will
work as a normal port and need no further initialization. To use the
A/D converter a single byte should be written to ADCON which
selects the A/D mux and concurrently sets the ADCS bit to start the
A/D conversion. The 40 machine cycles of the A/D conversion
include time for signal settling after the mux is selected and before
the Sample and Hold procedure is completed.
The circuitry which disables the digital buffer from the port pin is
updated at the start of an A/D conversion by setting the ADCS bit in
ADCON. After powerup, problems will occur the first time that
ADCON is written to if ADCS is not set; in this case, the digital
signal disable registers contain random data and some o the 8 port
pins will have their digital buffers disabled. When read, these
disabled buffers will ignore their input and only return a 1. This
condition will be corrected by writing a 1 to ADCS in ADCON which
starts and A/D conversion.
Thus, there are two operating modes:
1. DIGITAL ONLY - No Analog inputs are used and ADCON is
2. A/D CONVERTER USED - The input multiplexer select field
1998 May 01
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer
never written to. In this case pins ADC0-ADC7 are configured as
digital inputs.
must be written to and ADCS must be set in ADCON. This allows
unselected A/D inputs to be used as digital inputs.
CC
and Vref– is combined with AV
SS
. The analog
8
*Not present on 40-pin DIP versions.
ADCON Register
ADCI
Symbol Position
ADCI
ADCS
AADR2 ADCON.2
AADR1 ADCON.1
AADR0 ADCON.0
0
0
1
1
MSB
X
ADDR2
0
0
0
0
1
1
1
1
ADCON.4
ADCON.3
ADCS
X
0
1
0
1
INPUT CHANNEL SELECTION
ADC not busy, a conversion can be started.
ADC busy, start of a new conversion is blocked.
Conversion completed, start of a new is blocked.
Not possible.
X
ADDR1
ADC interrupt flag. This flag is set when an
ADC conversion is complete. If IE.5 = 1, an
interrupt is requested when ADCI = 1. The
ADCI flag must be cleared by software after
A/D data is read, before the next conversion
can begin.
ADC start and status. Setting this bit starts an
A/D conversion. Once set, ADCS remains high
throughout the conversion cycle. On
completion of the conversion, it is reset at the
same time the ADCI interrupt flag is set. ADCS
cannot be reset by software.
Analog input selects.
Binary coded address
selects one of the five analog input port pins of
P1 to be input to the converter. It can only be
changed when ADCI and ADCS are both low.
AADR2 is the most significant bit.
80C550/83C550/87C550
0
0
1
1
0
0
1
1
Operation
Function
ADCI
SDCS
ADDR0
0
1
0
1
0
1
0
1
AADR2
Product specification
AADR1
INPUT PIN
P1.6*
P1.7*
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
AADR0
LSB