p89lpc9402 NXP Semiconductors, p89lpc9402 Datasheet - Page 32

• Manufacturer Part Number: p89lpc9402
• Description: 8-bit Microcontroller With Accelerated Two-clock 80c51 Core 8 Kb 3 V Byte-erasable ?ash With 32 Segment 4 Lcd Driver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
P89LPC9402_1
Product data sheet
Fig 11. SPI block diagram
SPI STATUS REGISTER
BY 4, 16, 64, 128
CPU clock
DIVIDER
SELECT
SPI CONTROL
7.22 SPI
The P89LPC9402 provides another high-speed serial communication interface, the SPI
interface. SPI is a full-duplex, high-speed, synchronous communication bus with two
operation modes: Master mode and Slave mode. Up to 4.5 Mbit/s can be supported in
Master mode or up to 3 Mbit/s in Slave mode. It has a transfer completion flag and write
collision flag protection.
The SPI interface has three pins: SPICLK, MOSI, MISO and SS:
Typical connections are shown in
•
SPICLK, MOSI and MISO are typically tied together between two or more SPI
devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and flows
from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output
in the master mode and is input in the slave mode. If the SPI system is disabled, i.e.,
SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions.
interrupt
request
SPI clock (master)
SPI
MSTR
SPEN
internal
Rev. 01 — 22 April 2009
data
bus
8-bit microcontroller with accelerated two-clock 80C51 core
SPI CONTROL REGISTER
8-BIT SHIFT REGISTER
READ DATA BUFFER
CLOCK LOGIC
Figure 12
clock
through
Figure
14.
P89LPC9402
M
M
M
S
S
S
CONTROL
LOGIC
PIN
© NXP B.V. 2009. All rights reserved.
002aab466
MISO
P2.3
MOSI
P2.2
SPICLK
P2.5
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