p89lpc904 NXP Semiconductors, p89lpc904 Datasheet - Page 15

• Manufacturer Part Number: p89lpc904
• Description: 8-bit Microcontrollers With Two-clock Accelerated 80c51 Core 1 Kb 3 V Byte-erasable Flash With 8-bit A/d Converter
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 13521
Preliminary data
8.6 CPU CLock (CCLK) wake-up delay
8.7 CPU CLOCK (CCLK) modification: DIVM register
8.8 Low power select
The P89LPC904 has an internal wake-up timer that delays the clock until it stabilizes
depending to the clock source used.
The OSCCLK frequency can be divided down up to 510 times by configuring a
dividing register, DIVM, to generate CCLK. This feature makes it possible to
temporarily run the CPU at a lower rate, reducing power consumption. By dividing the
clock, the CPU can retain the ability to respond to events that would not exit Idle
mode by executing its normal program at a lower rate. This can also allow bypassing
the oscillator start-up time in cases where Power-down mode would otherwise be
used. The value of DIVM may be changed by the program at any time without
interrupting code execution.
If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to
lower the power consumption further. On any reset, CLKLP is logic 0.
Rev. 02 — 25 June 2004
8-bit microcontrollers with two-clock accelerated 80C51 core
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
P89LPC904
15 of 41