p89lpc930fdh NXP Semiconductors, p89lpc930fdh Datasheet - Page 31
p89lpc930fdh
Manufacturer Part Number
p89lpc930fdh
Description
8-bit Microcontrollers With Two-clock 80c51 Core 4 Kb/8 Kb 3 V Flash With 256-byte Data Ram
Manufacturer
NXP Semiconductors
Datasheet
1.P89LPC930FDH.pdf
(55 pages)
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8.19 Serial Peripheral Interface (SPI)
LPC930/931 provides another high-speed serial communication interface - the SPI
interface. SPI is a full-duplex, high-speed, synchronous communication bus with two
operation modes: Master mode and Slave mode. Up to 4.5 Mbit/s can be supported
in Master or 3.0 Mbit/s in Slave mode. It has a Transfer Completion Flag and Write
Collision Flag Protection.
Fig 8. I
P1.3/SDA
P1.2/SCL
2
C-bus serial interface block diagram.
Rev. 05 — 15 December 2004
OUTPUT
OUTPUT
FILTER
STAGE
FILTER
STAGE
INPUT
INPUT
P1.3
P1.2
STATUS BUS
OVERFLOW
TIMER 1
I2SCLH
I2SCLL
I2CON
8-bit microcontrollers with two-clock 80C51 core
I2STAT
ARBITRATION &
BIT COUNTER /
SERIAL CLOCK
SYNC LOGIC
GENERATOR
SCL DUTY CYCLE REGISTERS
ADDRESS REGISTER
CONTROL REGISTERS &
SHIFT REGISTER
DECODER
COMPARATOR
STATUS
STATUS REGISTER
P89LPC930/931
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8
CONTROL
TIMING
LOGIC
&
I2DAT
8
8
8
ACK
I2ADR
CCLK
INTERRUPT
002aaa421
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