at3210 Aimtron Technology, at3210 Datasheet - Page 7

• Manufacturer Part Number: at3210
• Description: 16 Grayscales 160x160 Stn Lcd Controller
• Manufacturer: Aimtron Technology

MPU interface
The Interpretation and execution of command depends on the external clock.
terminal for reading, and inputting a low pulse to the WR terminal for writing. In the 6800 series
MPU interface, the interface is placed in a read mode when an ‘H’ signal is input to the RW
terminal and placed in a write mode when a ‘L’ signal is input to the R/W terminal and then the
command is launched by inputting a high pulse to the E terminal. (See the timming diagram
regarding the timing.) When the serial interface is selected, the data is input in sequence
starting with D7.
interpretation of the data format depends on the DFORMAT command. If DFORMAT=0, the
high nibble is the first pixel and the low nibble is the second pixel. If DFORMAT=1, the high
nibble is the second pixel and the low nibble is the first pixel. If DFORMAT=2, the high nibble
is the current pixel data and the low nibble is don’t care. If DFORMAT=3, the low nibble is the
current pixel data and the high nibble is don’t care. Each MPU write cycle latches 2 pixel data
when DFORMAT=0 or 1and 1 pixel data when DFORMAT=2 or 3. See Fig.6 and Fig. 7. The
internal RAM will write these data only after 32 bits data is latched
DFORMAT. The read pulses of the MPU must be the multiples of 4 which is independant of
the DFORMAT. If you want to read data from memory, one dummy read cycle must be
asserted before the wanted data output. The first read/write data is determined by the internal
row and column counter. See Fig. 8.
The data bus is at input state when the AT3210 detects a write operation. The data bus is at
output state when the AT3210 detects a read operation. See Fig. 14. Note that the output state
after a read operation will hold until the next write operation is detected.
AIMTRON TECHNOLOGY CORP.
2F,NO.10, Prosperity Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C
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The chip identifies the data bus signals by a combination of RS, RD(E), WR(RW) signals.
In the 8080 MPU interface, commands are launched by inputting a low pulse to the RD
The MPU data bus is used as the display data input when the RS pin is ‘1’. The
The write pulses of the MPU must be the multiples of 4 or 8 which depends on the
The input/output direction of the MPU data bus is determined by the read/write operation.
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16 GrayScales 160X160 STN LCD Controller
Rev 1.11 Feb. 2002
7
Preliminary Product Information
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Homepage:http://www.aimtron.com.tw
AT3210