at91sam9x25-cu ATMEL Corporation, at91sam9x25-cu Datasheet - Page 38

• Manufacturer Part Number: at91sam9x25-cu
• Description: At91sam Arm-based Embedded Mpu
• Manufacturer: ATMEL Corporation

10.11 Ethernet 10/100 MAC (EMAC)
10.12 8-channel DMA (DMAC)
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SAM9X25
• Two EMACs
• EMAC0 supports MII Mode
• EMAC1 supports RMII Mode only
• Compatibility with IEEE Standard 802.3
• 10 and 100 Mbits per second data throughput capability
• Full- and half-duplex operations
• Register Interface to address, data, status and control registers
• DMA Interface, operating as a master on the Memory Controller
• Interrupt generation to signal receive and transmit completion
• 128-byte transmit and 128-byte receive FIFOs
• Automatic pad and CRC generation on transmitted frames
• Address checking logic to recognize four 48-bit addresses
• Support promiscuous mode where all valid frames are copied to memory
• Support physical layer management through MDIO interface
• Support Wake On Lan: The receiver supports Wake on LAN by detecting the following events
• Two DMACs
• DMAC0 is full featured and optimized for memory-to-memory transfers thanks to the 64-word
• DMAC1 is optimized for peripheral-to-memory transfers, without PIP support
• Acting as Two Matrix Masters
• Embeds 8 unidirectional channels with programmable priority
• Address Generation
on incoming receive frames:
FIFO on channel 0
– Magic packet
– ARP request to the device IP address
– Specific address 1 filter match
– Multicast hash filter match
– Source / destination address programming
– Address increment, decrement or no change
– DMA chaining support for multiple non-contiguous data blocks through use of linked
– Scatter support for placing fields into a system memory area from a contiguous
– Gather support for extracting fields from a system memory area into a contiguous
– User enabled auto-reloading of source, destination and control registers from initially
– Auto-loading of source, destination and control registers from system memory at end
lists
transfer. Writing a stream of data into non-contiguous fields in system memory
transfer
programmed values at the end of a block transfer
of block transfer in block chaining mode
11054AS–ATARM–29-Jul-11