attiny15l ATMEL Corporation, attiny15l Datasheet - Page 23

• Manufacturer Part Number: attiny15l
• Description: Attiny15l 8-bit Microcontroller With 1k Byte Flash
• Manufacturer: ATMEL Corporation

Sleep Modes
Idle Mode
1187H–AVR–09/07
• Bits 4, 3 – SM1, SM0: Sleep Mode Select Bits 1 and 0
These bits select between the three available sleep modes, as shown in Table 7.
Table 7. Sleep Modes
For details, refer to “Sleep Modes” below.
• Bit 2 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny15L and always reads as zero.
• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the
corresponding interrupt mask is set (one). The activity on the external INT0 pin that acti-
vates the interrupt is defined in Table 8:
Table 8. Interrupt 0 Sense Control
Note:
To enter any of the three sleep modes, the SE bit in MCUCR must be set (one) and a
SLEEP instruction must be executed. The SM1 and SM0 bits in the MCUCR Register
select which sleep mode (Idle, ADC Noise Reduction or Power-down) will be activated
by the SLEEP instruction (see Table 7). If an enabled interrupt occurs while the MCU is
in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles, executes
the interrupt routine and resumes execution from the instruction following SLEEP. On
wake-up from Power-down mode on pin change, two instruction cycles are executed
before the Pin Change Interrupt Flag is updated. The contents of the Register File,
SRAM, and I/O memory are unaltered when the device wakes up from sleep. If a reset
occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.
When the SM1/SM0 bits are “00”, the SLEEP instruction forces the MCU into the Idle
mode, stopping the CPU but allowing the ADC, Analog Comparator, Timer/Counters,
Watchdog and the Interrupt system to continue operating. This enables the MCU to
wake-up from external triggered interrupts as well as internal ones like the Timer Over-
flow Interrupt and Watchdog Reset. If the ADC is enabled, a conversion starts
automatically when this mode is entered. If wake-up from the Analog Comparator inter-
rupt is not required, the Analog Comparator can be powered down by setting the ADC-
bit in the Analog Comparator Control and Status Register (ACSR). This will reduce
ISC01
SM1
0
0
1
1
0
0
1
1
1. When changing the ISC10/ISC00 bits, INT0 must be disabled by clearing its Interrupt
Enable bit in the GIMSK Register. Otherwise an interrupt can occur when the bits are
changed.
SM0
ISC00
0
1
0
1
0
1
0
1
Sleep Mode
Idle mode
ADC Noise Reduction mode
Power-down mode
Reserved
Description
The low level of INT0 generates an interrupt request.
Any change on INT0 generates an interrupt request
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
power consumption in Idle mode.
(1)
ATtiny15L
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