attiny24v ATMEL Corporation, attiny24v Datasheet - Page 25
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attiny24v
Manufacturer Part Number
attiny24v
Description
8-bit Avr Microcontroller With 2/4/8k Bytes Insystem Programmable Flash
Manufacturer
ATMEL Corporation
Datasheet
1.ATTINY24V.pdf
(236 pages)
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6.1.2
6.1.3
6.1.4
6.2
8006H–AVR–10/09
Clock Sources
I/O Clock – clk
Flash Clock – clk
ADC Clock – clk
I/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is
also used by the External Interrupt module, but note that some external interrupts are detected
by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted.
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-
taneously with the CPU clock.
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
The device has the following clock source options, selectable by Flash Fuse bits as shown
below. The clock from the selected source is input to the AVR clock generator, and routed to the
appropriate modules.
Table 6-1.
Note:
The various choices for each clocking option is given in the following sections. When the CPU
wakes up from Power-down the selected clock source is used to time the start-up, ensuring sta-
ble Oscillator operation before instruction execution starts. When the CPU starts from reset,
there is an additional delay allowing the power to reach a stable level before commencing nor-
mal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up time.
The number of WDT Oscillator cycles used for each time-out is shown in
Table 6-2.
ADC
Device Clocking Option
External Clock (see
Reserved
Calibrated Internal 8 MHz Oscillator (see
Reserved
Internal 128 kHz Oscillator (see
Reserved
Low-Frequency Crystal Oscillator (see
Reserved
Crystal Oscillator / Ceramic Resonator (see
FLASH
1. For all fuses “1” means unprogrammed and “0” means programmed.
Typ Time-out
Device Clocking Options Select
Number of Watchdog Oscillator Cycles
64 ms
4 ms
page
26)
page
27)
page
page
page
28)
26)
28)
Number of Cycles
8K (8,192)
512
ATtiny24/44/84
Table
CKSEL3:0
1000-1111
6-2.
0000
0001
0010
0011
0100
0101
0110
0111
(1)
25
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