hcs10ms Intersil Corporation, hcs10ms Datasheet

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hcs10ms

Manufacturer Part Number
hcs10ms
Description
Radiation Hardened Triple 3-input Nand Gate
Manufacturer
Intersil Corporation
Datasheet
September 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
• Cosmic Ray Upset Immunity < 2 x 10
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
• Input Current Levels Ii
Description
The Intersil HCS10MS is a Radiation Hardened Triple 3-Input
NAND Gate. A high on all inputs forces the output to a Low state.
The HCS10MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS10MS is supplied in a 14 lead Ceramic flatpack (K suffix)
or a SBDIP Package (D suffix).
Ordering Information
HCS05DMSR
HCS05KMSR
HCS05D/
Sample
HCS05K/
Sample
HCS05HMSR
(Typ)
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
NUMBER
PART
TEMPERATURE
-55
-55
o
o
RANGE
C to +125
C to +125
+25
+25
+25
10
o
o
o
C
C
C
RAD (SI)/s 20ns Pulse
5 A at VOL, VOH
o
o
C
C
Intersil Class
S Equivalent
Intersil Class
S Equivalent
Sample
Sample
Die
SCREENING
12
o
LEVEL
C to +125
RAD (Si)/s
-9
Errors/Gate Day (Typ)
o
-9
C
14 Lead SBDIP
14 Lead Ceramic
Flatpack
14 Lead SBDIP
14 Lead Ceramic
Flatpack
Die
2
/mg
Errors/Bit-Day
PACKAGE
1
Pinouts
Functional Diagram
NOTE: L = Logic Level Low, H = Logic level High
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) MIL-STD-183S CDFP3-F14, LEAD FINISH C
(5, 11, 13)
GND
(2, 4, 10)
(1, 3, 9)
A1
B1
A2
B2
C2
Y2
An
Bn
Cn
An
H
H
H
H
L
L
L
L
MIL-STD-183S CDIP2-T14, LEAD FINISH C
HCS10MS
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
GND
INPUTS
A1
B1
A2
B2
C2
Y2
Triple 3-Input NAND Gate
Bn
H
H
H
H
L
L
L
L
1
2
3
4
5
6
7
TRUTH TABLE
1
2
3
4
5
6
7
TOP VIEW
TOP VIEW
Radiation Hardened
Cn
H
H
H
H
L
L
L
L
Spec Number
14
13
12
11
10
9
8
File Number
14
13
12
11
10
9
8
VCC
C1
Y1
C3
B3
A3
Y3
OUTPUTS
Yn
H
H
H
H
H
H
H
L
(12, 6, 8)
518747
2435.2
Yn
VCC
C1
Y1
C3
B3
A3
Y3

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hcs10ms Summary of contents

Page 1

... NAND Gate. A high on all inputs forces the output to a Low state. The HCS10MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCS10MS is supplied lead Ceramic flatpack (K suffi SBDIP Package (D suffix). Ordering Information PART ...

Page 2

... Functional Test VIH = 0.70(VCC), VIL = 0.30(VCC) (Note 2) NOTES: 1. All voltages reference to device GND. 2. For functional tests, VO 4.0V is recognized as a logic “1”, and VO Specifications HCS10MS Reliability Information Thermal Resistance SBDIP Package 10mA Ceramic Flatpack Package . . . . . . . . . . . 25mA Maximum Package Power Dissipation at +125 SBDIP Package ...

Page 3

... VCC = 4.5V TPLH VCC = 4.5V NOTES: 1. All voltages referenced to device GND measurements assume RL = 500 , CL = 50pF, Input 3ns, VIL = GND, VIH = VCC. 3. For functional tests, VO 4.0V is recognized as a logic “1”, and VO Specifications HCS10MS GROUP (NOTES SUB- CONDITIONS GROUPS TEMPERATURE 9 ...

Page 4

... Alternate Group A testing in accordance with Method 5005 of MIL-STD-883 may be exercised. 2. Table 5 parameters only. CONFORMANCE GROUPS METHOD Group E Subgroup 2 5005 NOTE: 1. Except FN test which will be performed 100% Go/No-Go. Specifications HCS10MS GROUP B SUBGROUP DELTA LIMIT 5 5 -15 Hour TABLE 6. APPLICABLE SUBGROUPS METHOD GROUP A SUBGROUPS ...

Page 5

... Each pin except VCC and GND will have a resistor of 10K 2. Each pin except VCC and GND will have a resistor of 1K OPEN NOTE: Each pin except VCC and GND will have a resistor of 47K Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures. Specifications HCS10MS 1/2 VCC = 3V 0.5V VCC = ...

Page 6

... Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. • The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. HCS10MS 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition hrs ...

Page 7

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com HCS10MS AC Load Circuit TPHL ...

Page 8

... Thickness: 13k 2.6k WORST CASE CURRENT DENSITY <2 A/cm BOND PAD SIZE: 100 m x 100 mils Metallization Mask Layout B1 (2) A2 (3) B2 (4) C2 (5) HCS10MS HCS10MS A1 VCC C1 (1) (14) (13) (6) (7) (8) Y2 GND Y3 8 (12) Y1 (11) C3 (10) B3 (9) A3 518747 Spec Number ...

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