lm78ccvf National Semiconductor Corporation, lm78ccvf Datasheet - Page 3

• Manufacturer Part Number: lm78ccvf
• Description: Microprocessor System Hardware Monitor
• Manufacturer: National Semiconductor Corporation

IORD
IOWR
SYSCLK
D7–D0
V
GNDD
SMI__IN
Chassis
Intrusion
Power
Switch
Bypass
FAN3–FAN1
SCL
SDA
RESET
NTEST
GNDA
−IN6
FB6
FB5
−IN5
IN4–IN0
VID3–VID0
BTI
NMI/IRQ
SMI
CC
Pin Descriptions
Name(s)
(+5V)
Pin
Number
17–19
29–33
34–37
4–11
Pin
12
13
14
15
16
20
21
22
23
24
25
26
27
28
38
39
40
1
2
3
Number
of Pins
1
1
1
8
1
1
1
1
1
3
1
1
1
1
1
1
1
1
1
5
4
1
1
1
Digital Input
Digital Input
Digital Input
Digital I/O
POWER
GROUND
Digital Input
Digital I/O
Digital Output
Digital Input
Digital Input
Digital I/O
Digital Output
Test Output
GROUND
Analog Input
Analog Output
Analog Output
Analog Input
Analog Input
Digital Input
Digital Input
Digital Output
Digital Output
Type
An active low standard ISA bus I/O Read Control.
An active low standard ISA bus I/O Write Control.
The reference clock for the ISA bus. Typically ranges from 4.167 MHz to
8.33 MHz. The minimum clock frequency this input can handle is 1 Hz.
Bi-directional ISA bus Data lines. D0 corresponds to the low order bit,
with D7 the high order bit.
+5V V
Chainable SMI (System Management Interrupt) Input. This is an active
low input that propagates the SMI signal to the SMI output of the LM78
via SMI Mask Register Bit 6 and SMI enable Bit 1 of the Configuration
Register.
Intrusion event. This line can go high without any clamping action
regardless of the powered state of the LM78. The LM78 provides an
internal open drain on this line, controlled by Bit 7 of NMI Mask Register
2, to provide a minimum 20 ms reset of this line.
An active low push-pull output intended to drive an external P-channel
power MOSFET for software power control.
0V to +5V amplitude fan tachometer input.
Serial Bus Clock.
Serial Bus bidirectional Data.
Master Reset, 5 mA driver (open drain), active low output with a 20 ms
minimum pulse width. Available when enabeld via Bit 7 in SMI Mask
Register 2.
testing. Refer to Section 11.0 on NAND Tree testing.
analog inputs.
INPUTS”.
INPUTS”.
INPUTS”.
0V to 4.096V FSR Analog Inputs.
Voltage Supply readouts from P6. This value is read in the VID/Fan
Divisor Register.
Board Temperature Interrupt driven by O.S. outputs of additional
temperature sensors such as LM75. Provides internal pull-up of 10 k .
Non-Maskable Interrupt (open source)/Interrupt Request (open drain).
The mode is selected with Bit 5 of the Configuration Register and the
output is enabled when Bit 2 of the Configuration Register is set to 1.
The default state is disabled and IRQ mode.
System Management Interrupt (open drain). This output is enabled when
Bit 1 in the Configuration Register is set to 1. The default state is
disabled.
(electolytic or tantalum) and 0.1 µF (ceramic) bypass capacitors.
Internally connected to all digital circuitry.
An active high input from an external circuit which latches a Chassis
NAND Tree totem-pole output that provides board-level connectivity
Internally connected to all analog circuitry. The ground reference for all
Ground-referred inverting op amp input. Refer to Section 4.0, “ANALOG
Output of inverting op amp for Input 6. Refer to section 4.0, “ANALOG
Output of inverting op amp for Input 5. Refer to section 4.0, “ANALOG
Ground-referred inverting op amp input. Refer to Section 4.0, “ANALOG
INPUTS”.
CC
3
power. Bypass with the parallel combination of 10 µF
Description
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