a8286 Allegro MicroSystems, Inc., a8286 Datasheet - Page 16

• Manufacturer Part Number: a8286
• Description: Dual Lnb Supply And Control Voltage Regulator
• Manufacturer: Allegro MicroSystems, Inc.

A8286
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
DIS1
DIS2
OCP1
OCP1
PNG1
PNG2
TSD
VUV
Table 6. Status Register 1
LNB Output Disabled. DIS is used to indicate the current condition of the LNB
output for channel 1. At power-on, or if a fault condition occurs, DIS1 is set. This
bit changing to 1 does not cause the IRQ to activate because the LNB output may
be disabled intentionally by the I
write sequence if the LNB output is enabled.
See description for DIS1. This indicates status for channel 2.
Overcurrent. If the LNB output detects an overcurrent condition for greater than
48 ms the LNB output will be disabled. The OCP bit will be set to indicate that an
overcurrent has occurred and the disable bit, DIS1, will be set. The Status register
is updated on the rising edge of the 9
the OCP bit is reset in all cases, allowing the master to reenable the LNB output.
See description for OCP1. This indicates status for channel 2.
Power Not Good. Set to 1 when the LNB output is enabled and the LNB voltage
is below 85 % of the programmed voltage. PNG1 is reset when the LNB volts are
within 90 % of the programmed LNB voltage.
See description for PNG1. This indicates status for channel 2.
Thermal shutdown. 1 indicates that the A8286 has detected an overtemperature
condition and has disabled the LNB outputs. The disable bits, DISx, will also be
set. The status of the overtemperature condition is sampled on the rising edge of
the 9
then the TSD bit will be reset, allowing the master to reenable the LNB output if
required. If the condition is still present, then the TSD bit will remain at 1.
Undervoltage Lockout. 1 indicates that the A8286 has detected that the input sup-
ply, V
occurred disabling the LNB outputs. The disable bits, DISx, will also be set, and the
A8286 will not reenable the output until so instructed by writing the relevant bit into
the control registers. The status of the undervoltage condition is sampled on the ris-
ing edge of the 9
ger present, then the VUV bit will be reset allowing the master to reenable the LNB
output if required. If the condition is still present, then the VUV bit will remain at 1.
Dual LNB Supply and Control Voltage Regulator
Bit
0
1
2
3
4
5
6
7
th
IN
clock pulse in the data read sequence. If the condition is no longer present,
is, or has been, below the minimum level and an undervoltage lockout has
Name
OCP1
OCP2
PNG1
PNG2
DIS1
DIS2
TSD
VUV
th
clock pulse in the data read sequence. If the condition is no lon-
LNB output disabled (Channel 1)
LNB output disabled (Channel 2)
Power Not Good (Channel 1)
Power Not Good (Channel 2)
Overcurrent (Channel 2)
Overcurrent (Channel 1)
2
Thermal Shutdown
V
C™ master. This bit will be reset at the end of a
IN
th
Undervoltage
Function
clock pulse in the data read sequence, where
115 Northeast Cutoff, Box 15036
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com
16