lnbh23qtr STMicroelectronics, lnbh23qtr Datasheet - Page 18

• Manufacturer Part Number: lnbh23qtr
• Description: Lnbs Supply And Control Ic With Step-up And I??c Interface
• Manufacturer: STMicroelectronics

Table 7.
1. Values are typical unless otherwise specified
2. IMON information must be disregarded if 22 kHz TONE output is enabled
3. VMON information must be disregarded if LLC=1 (valid only if LLC=0)
7.5
7.6
7.7
18/32
0/1
IMON
(2)
VMON
0/1
Register
Power-ON I²C interface reset
I²C interface built in LNBH23 is automatically reset at power-on. As long as the V
below the undervoltage lockout (UVL) threshold (6.7 V), the interface does not respond to
any I²C command and the system register (SR) is initialized to all zeroes, thus keeping the
power blocks disabled. Once the V
operative and the SR can be configured by the main MCU. This is due to 500 mV of
hysteresis provided in the UVL threshold to avoid false retriggering of the power-on reset
circuit.
Address pin
It is possible to select two I²C interface addresses by means of ADDR pin. This pin is TTL
compatible and can be set as per hereafter address pin characteristics
DiSEqC
LNBH23 helps system designer to implement bi-directional DiSEqC 2.0 protocol by allowing
an easy PWK modulation/demodulation of the 22 kHz carrier. Between the LNBH23 and the
main MCU the PWK data is exchanged using logic levels that are compatible with both 3.3 V
and 5 V MCU. This data exchange is made through two dedicated pins, DSQIN and
DSQOUT, in order to maintain the timing relationships between the PWK data and the PWK
modulation as accurate as possible. These two pins should be directly connected to two I/O
pins of the MCU, thus leaving to the firmware the task of encoding and decoding the PWK
data in accordance to the DiSEqC protocol.
Full compliance of the system to the specification is thus not implied by the bare use of the
LNBH23. The system designer should also take in consideration the bus hardware
requirements; that can be simply accomplished by the R-L termination connected between
V
avoid any losses due to the R-L impedance during the tone transmission, LNBH23 has
dedicated Tone output (V
setting the TTX function to HIGH only during the tone transmission (see DiSEqC 2.0
operation implementation in section
DiSEqC systems need this termination connected through a bypass capacitor and after a R-
L filter with 15 Ω in parallel with a 220 µH-270 µH inductor but, there is no need of Tone
Decoding, thus DETIN and DSQOUT pins can be left connected to GND.
(3)
oRX
and V
TMON
0/1
oTX
TM
LLC
exactly the same as
These bits are read
last write operation
they were left after
pins of LNBH23, as shown in the typical application circuit in
implementation
VSEL
oTX
) that is connected after the filter and must be enabled by
EN
CC
OTF
2.2
0
1
rises above 7.3 V typ. The I²C interface becomes
and 2.3). Also unidirectional DiSEqC 1.x and non-
OLF
0
1
T
T
I
I
These bits are set to 1 if the relative parameter
is out of the specification limits.
O
O
J
J
< I
> I
< 135°C, normal operation
> 150°C, power blocks disabled
OMAX
OMAX
, normal operation
, Overload Protection triggered
Function
Table
(1)
Figure
10.
(1)
CC
4. To
stays