NBSG53AMNR2 ON Semiconductor, NBSG53AMNR2 Datasheet - Page 3

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NBSG53AMNR2

Manufacturer Part Number
NBSG53AMNR2
Description
IC FLIP FLOP DIFF CLOCK 16QFN
Manufacturer
ON Semiconductor
Type
D-Type Busr
Datasheet

Specifications of NBSG53AMNR2

Function
Reset
Output Type
Differential
Number Of Elements
1
Number Of Bits Per Element
2
Frequency - Clock
8GHz
Trigger Type
Positive, Negative
Voltage - Supply
2.375 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-TQFN Exposed Pad
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Current - Output High, Low
-
Delay Time - Propagation
-
Other names
NBSG53AMNR2OSTR
Table 2. OUTPUT LEVEL SELECT (OLS)
4. When an output level of 400 mV is desired and
Table 4. INTERFACING OPTIONS
INTERFACING OPTIONS
RSECL, PECL, NECL
V
OLS to V
V
V
V
V
CC
LVTTL, LVCMOS
EE
AC−COUPLED
CC
CC
CC
Float
− V
VTCLK
VTCLK
OLS
V
(Note 4)
− 0.4 V
− 0.8 V
− 1.2 V
CC
LVDS
OLS
VTD
VTD
CML
CLK
CLK
SEL
EE
EE
D
D
R
> 3.0 V, 2.0 kW resistor should be connected from
.
Q/Q VPP
800 mV
200 mV
600 mV
400 mV
600 mV
0
V
50 W
50 W
50 W
50 W
THR
An External Voltage (V
75 kW
is 1.5 V for LVTTL and V
V
V
CC
Bias VTCLK, VTD and VTCLK, VTD Inputs within Common Mode Range (V
OLS Sensitivity
EE
OLS $ 150 mV
OLS $ 100 mV
OLS + 100 mV
OLS $ 75 mV
OLS − 75 mV
75 kW
Figure 3. Simplified Logic Diagram
N/A
2
2
2
THR
D
D
http://onsemi.com
Flip−Flop
Flip−Flop
) should be Applied to the Unused Complementary Differential Input. Nominal
Connect VTCLK, VTD and VTCLK, VTD Together
(DIV/2)
Connect VTCLK, VTD and VTCLK, VTD to V
(DFF)
CC
R
R
/2 for LVCMOS Inputs. This Voltage must be within the V
2
Standard ECL Termination Techniques
Q
Q
3
Table 3. TRUTH TABLE
Z = LOW to HIGH Transition
R
H
CONNECTIONS
L
L
L
2
2
SEL
H
H
L
x
D
H
x
L
x
1
0
CLK
x
Z
Z
Z
2
CC
Q
H
Q
L
L
IHCMR
Function
THR
Reset
DIV/2
DFF
DFF
Q
Q
)
Specification.

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