tmp19a43fd TOSHIBA Semiconductor CORPORATION, tmp19a43fd Datasheet - Page 80
tmp19a43fd
Manufacturer Part Number
tmp19a43fd
Description
32-bit Risc Microprocessor
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP19A43FD.pdf
(105 pages)
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Quantity
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Note 1:w No. 1 to 21ú
No.
10
11
12
13
14
15
16
17
18 D0-D15
19
20
21
1
2
3
4
5
6
7
8
9
negated
ALE width = 1 clock cycles, 2 programmed wait state
System clock period (x)
A0-A15 VALID TO ALE LOW
A0-A15 HOLD AFTER ALE LOW
ALE pulse width high
ALE low to
asserted
high
A0-A15 valid to
asserted
A16-A23 valid to
asserted
A16-A23 hold after
A0-A15 valid to D0-D15 Data in
A16-A23 valid to D0-D15 Data in
D0-D15 hold after
WR
D0-D15 valid to
negated
A16-A23 valid to
A0-A15 valid to
asserted
RD
HWR
RD
RD
RD
w w w TW = W + 2N
WAIT
/ HWR
,
negated to next A0-A15 output
asserted to D0-D15 data in
WR
width low
negated
hold after
hold
Internal 2 wait insertion ìALE p1q Clockì@40MHz
AC measurement conditions:
or
W : Number of Auto wait insertion
RD
Output levels:
Input levels:
Parameter
width low
TW = 2 + 2*1 = 4
HWR
,
after
WAIT
WR
WR
WAIT
RD
RD
RD
RD
,
or
negated to ALE
,
,
or
WR
input
RD
negated
WR
input
WR
WR
HWR
HWR
,
or
or
or
or
WR
HWR
HWR
HWR
HWR
High = 0.7DVCC3 V/Low 0.3DVCC3 V
High = 0.8DVCC3 V/Low 0.2DVCC3 V, CL = 30 pF
or
,
Symb
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SYS
AL
LA
LL
LC
CL
ACL
ACH
CAR
ADL
ADH
RD
RR
HR
RAE
WW
DW
WD
AWH
AWL
CW
ol
TMP19A43 5-9
x (1
x (1
x (1
(TW - 3)-16
2x
2x
x
x
x –11
x – 8
x – 6
x – 8
x
Min
x 6
TW)
25
TW)
TW) 6
0
11
11
, 2N : Number of external wait insertion
8
11
11
11
6
Equation
x (2
x (2
x+ x (ALE)×(TW-
x+ x (ALE)×(TW-
(TW – 1) – 29
x (1
TW+ALE)
TW+ALE)
1)Ù32
1)Ù32
Max
TW) 40
43
43
TMP19A43
Min
14.0
17.0
19.0
17.0
17.0
39.0
39.0
14.0
19.0
69.0
64.0
14.0
9.0
(fsys)(Note)
69
0
40 MHz
Max
82.0
82.0
35.0
43.0
43.0
46.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns