tmp19a43fd TOSHIBA Semiconductor CORPORATION, tmp19a43fd Datasheet - Page 58

• Manufacturer Part Number: tmp19a43fd
• Description: 32-bit Risc Microprocessor
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Address
Normal
commands
Block erase
Auto
page
program-
ming
ID-READ
Protection
bit
program-
ming
Protection
bit erase
(Note)
(Note)
(Note)
Table 20.5.1.2 "Flash Memory Access from the Internal CPU" can also be used.
Address setting can be performed according to the "Normal bus write cycle address
configuration" from the first bus cycle.
""0" is recommended" can be changed as necessary.
(5) Address bit configuration for bus write cycles
PBA: Protection bit address (Set the seventh bus write cycle address for protection bit programming)
Flash area
Flash area
PA: Program page address (Set the fourth bus write cycle address for page programming operation)
Flash area
Flash area
Flash area
Flash area
[31:21]
Addr
PBA: Protection bit address (Set the seventh bus write cycle address for protection bit erasure)
BA: Block address (Set the sixth bus write cycle address for block erase operation)
"0" is recommended
"0" is recommended
Addr
[20]
IA: ID address (Set the fourth bus write cycle address for ID-Read operation)
Table 20.5.1.3 Address Bit Configuration for Bus Write Cycles
"0" is recommended
"0" is recommended
"0" is recommended
"0" is recommended
Addr
[19]
selection
selection
[18:17]
Block
Block
Normal bus write cycle address configuration
Addr
TMP19A43 (rev2.0)3-44
Addr
[16]
Protection bit write
00: Block 0
01: Block 1
10: Block 2
11: Block 3
Erase protection
for
0: Blocks 0, 1
1: Blocks 2, 3
Addr
[15]
ID address
Page selection
Addr[1:0]=0 (fixed), Others: 0 (recommended)
Addr
[14]
Command
Addr[1:0]=0 (fixed), Others: 0 (recommended)
Addr
[13]
Addr[1:0]=0 (fixed), Others: 0 (recommended)
Addr[1:0]=0 (fixed), Others: 0 (recommended)
[12:9]
Addr
Flash Memory Operation
TMP19A43
Addr[1:0]=0 (fixed), Others: 0
(recommended)
Addr
[8]
Addr [1:0]=0 (fixed),
Others: 0
(recommended)
[7:0]
Addr