lm7001jm Sanyo Semiconductor Corporation, lm7001jm Datasheet - Page 7
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lm7001jm
Manufacturer Part Number
lm7001jm
Description
Direct Pll Frequency Synthesizers For Electronic Tuning
Manufacturer
Sanyo Semiconductor Corporation
Datasheet
1.LM7001JM.pdf
(8 pages)
(4) R0 to R2: Reference frequency data
(5) S: Divider selection data
Notes on PLL IC Usage
1. PLL IC printed circuit board patterns
2. Initial states of the output ports (BO1 to BO3)
Note: The values listed for BO1, BO2, and BO3 are for the case when the B0 to B2 data is set to all zeros.
1: FMIN, 0: AMIN
The initial states of the output ports after power is applied are undefined until data has been transferred.
In particular, it is possible for the BO1 and BO3 pins to output the internal clock, so data must be transferred as soon
as possible.
However, note that the LSI cannot accept data until the crystal oscillator is operating normally.
R0
Power supply pins
A capacitor must be inserted between the V
must be located as close as possible to these pins.
FMIN and AMIN pins
The coupling capacitors must be located as close as possible to these pins.
PD pins, low-pass filter
Since those are high-impedance pins, they are susceptible to noise. Therefore, the pattern should be kept as short
as possible and the area around this circuit should be covered by the ground pattern.
0
0
0
0
1
1
1
1
R1
0
0
1
1
0
0
1
1
R2
0
1
0
1
0
1
0
1
f
100
ref [
50
25
10
5
9
1
5
kHz]
BO1
1
1
1
0
1
1
0
0
BO2
1
1
1
0
0
0
1
0
LM7001J, 7001JM
DD
and V
BO3
0
1
1
1
1
1
0
0
SS
power supply pins for noise exclusion. This capacitor
No. 5262-7/8