W83194R-37/-58 Winbond Electronics Corp America, W83194R-37/-58 Datasheet - Page 17

• Manufacturer Part Number: W83194R-37/-58
• Description: 100MHz/133MHz Via MVP3, Via Apollo Pro Clock Gen., 3-DIMM, With S.S.T.
• Manufacturer: Winbond Electronics Corp America

11.0 OPERATION OF DUAL FUCTION PINS
Pins 2, 7, 8, 25, and 26 are dual function pins and are used for selecting different functions in this
device (see Pin description). During power up, these pins are in input mode (see Fig1), therefore,
and are considered input select pins. When Vdd reaches 2.5V, the logic level that is present on
these pins are latched into their appropriate internal registers. Once the correct information are
properly latched, these pins will change into output pins and will be pulled low by default. At the end
of the power up timer (within 3 ms) outputs starts to toggle at the specified frequency.
Each of these pins are a large pull-up resistor ( 250 kΩ @3.3V ) inside. The default state will be logic
1, but the internal pull-up resistor may be too large when long traces or heavy load appear on these
dual function pins.
connected to Vdd if logic 1 is expected. Otherwise, the 10 kΩ resistor is connected to ground if a logic
0 is desired. The 10 kΩ resistor should be place before the serious terminating resistor. Note that
these logic will only be latched at initial power on.
If optional EMI reducing capacitor are needed, they should be placed as close to
terminating resistor as possible and after the series terminating resistor. These capacitor has typical
values ranging from 4.7pF to 22pF.
#2 REF0/CPU3.3#_2.5
#7 PCICLK_F/FS1
#8 PCICLK0/FS2
#25 24/MODE
#26 48/FS0
All other clocks
- 17 -
Under these conditions, an external 10 kΩ resistor is recommended to be
Output
tri-state
Output
tri-state
Input
2.5V
Output
pull-low
Output
pull-low
Within 3ms
Output
Publication Release Date: Sep 1998
Vdd
Revision 1.0
the series