stm6504seabdg6f STMicroelectronics, stm6504seabdg6f Datasheet - Page 5

• Manufacturer Part Number: stm6504seabdg6f
• Description: Dual Push-button Smart Reset Tm With User-adjustable Setup Delays
• Manufacturer: STMicroelectronics

STM6502, STM6503, STM6504, STM6505
1
Description
The Smart Reset™ devices provide a useful feature that ensures that inadvertent short
reset push-button closures do not cause system resets as the extended Smart Reset™
delay setup periods are implemented. Once the valid Smart Reset™ input levels and setup
delay are met, the device generates an output reset pulse for a fixed timeout period (t
The typical application hookup shows that either the single Smart Reset™ input or the dual
reset inputs are also connected to the applications interrupt and control both the interrupt
pin and the hard reset functions. If the push-button is closed for a short time, the processor
is only interrupted. If the system still does not respond properly, holding the push-button(s)
for the extended setup time (t
feature helps significantly increase system stability and eliminates the need for a dedicated
reset button.
The STM65xx family of Smart Reset™ devices consists of low-current microprocessor reset
circuits targeted at applications such as MP3 players, portable navigation devices or mobile
phones, generally any application that requires delayed reset push-button(s) response for
improved system stability. The delayed Smart Reset™ setup time (t
adding an external capacitor or selectable by three-state logic from the pre-defined options
of 2 s, 6 s and 10 s (all min.), see
shorter than t
The STM65xx devices have an active-low open-drain reset (RST) output with or without the
power-on reset function.
For the entire STM65xx Smart Reset™ family, the reset output is also asserted when the
monitored supply voltage V
remains asserted for the reset timeout period (t
above the specified threshold.
STM6502 has two combined Smart Reset™ inputs (SR0 and SR1) with delayed Smart
Reset™ setup time (t
STM6503 is similar to STM6502, has two combined delayed Smart Reset™ inputs (SR0,
SR1) and three user-selectable delayed Smart Reset™ setup time (t
and 10 s through a three-state TSR input pin: when connected to ground, t
left open, t
STM6504 has two independent Smart Reset™ inputs. SR0 provides the delayed Smart
Reset™ setup time (t
state TSR input pin: when connected to ground, t
connected to V
is edge-triggered with a special debounce time (t
edge after a valid reset period.
STM6505 has two combined delayed Smart Reset™ inputs (SR0, SR1) and provides an
adjustable reset delay setup time via an external capacitor connected to the SRC pin.
The RST output depends also on the V
independent low battery detect (BLD) output controlled by the secondary external input
voltage V
low detect output pin (BLD). V
is to be used to set the actual battery voltage threshold. V
typ. (16 mV max.). V
the V
CC
pin; V
BAT
SRC
. V
SRC
CC
= 6 s; when connected to V
CC
BAT
, thus preventing undesired resets.
, t
must be ≥ 1.575 V for proper operation of the V
is monitored for low voltage and provides an indication on the battery
SRC
BAT
SRC
SRC
= 10 s (all the times are minimum). SRE provides instant reset. SRE
is voltage monitoring input only, the device is powered only from
) programmed by an external capacitor on the SRC pin.
) function with three user-selectable t
CC
SRC
BAT
Doc ID 16101 Rev 4
drops below the specified threshold. The reset output
) causes a hard reset of the processor. The Smart Reset™
Table
threshold is 1.25 V, fixed, and an external resistor divider
CC
1. The delayed setup period ignores switch closures
CC
monitoring threshold. STM6505 also provides
, t
REC
SRC
SRC
DEBOUNCE
) after the monitored supply voltage goes
= 10 s (all the times are minimum).
= 2 s; when left open, t
BAT
= 240 ms min.) at the falling
threshold hysteresis is 8 mV
SRC
BAT
options through a three-
SRC
SRC
comparator.
) is adjustable by
) options of 2 s, 6 s
SRC
SRC
Description
= 2 s; when
= 6 s; when
REC
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).