W83194R-17/-17A Winbond Electronics Corp America, W83194R-17/-17A Datasheet - Page 16

• Manufacturer Part Number: W83194R-17/-17A
• Description: 100MHz Sis 5595, 5598 Clock Gen.
• Manufacturer: Winbond Electronics Corp America

10.0 POWER MANAGEMENT TIMING
10.1 CPU_STOP# Timing Diagram
For synchronous Chipset, CPU_STOP# pin is a synchronous “ active low ” input pin used to stop the
CPU clocks for low power operation. This pin is asserted synchronously by the external control logic
at the rising edge of free running PCI clock (PCICLK_F). All other clocks will continue to run while
the CPU clocks are stopped. The CPU clocks will always be stopped in a low state and resume
output with full pulse width. In this case, CPU locks on latency“ is less than 2 CPU clocks and
10.2 PCI_STOP# Timing Diagram
For synchronous Chipset, PCI_STOP# pin is a synchronous ctive low” input pin used to stop the
PCICLK [0:4] for low power operation. This pin is asserted synchronously by the external control
logic at the rising edge of free running PCI clock (PCICLK_F). All other clocks will continue to run
while the PCI clocks are stopped.
output with full pulse width. In this case, PCI locks on latency“ is less than 1 PCI clocks and
locks off latency” is less then 2 CPU clocks.
locks off latency” is less then 1 PCI clocks.
CPUCLK[0:3]
CPU_STOP#
PCI_STOP#
PCICLK[0:4]
PCICLK_F
PCICLK_F
CPUCLK
CPUCLK
(Internal)
(Internal)
(Internal)
(Internal)
PCICLK
PCICLK
SDRAM
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1
The PCI clocks will always be stopped in a low state and resume
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2
1
1
Publication Release Date: Sep. 1998
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Revision 1.0