tmp86c847iug TOSHIBA Semiconductor CORPORATION, tmp86c847iug Datasheet - Page 71

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tmp86c847iug

Manufacturer Part Number
tmp86c847iug
Description
8 Bit Microcontroller
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
7.3.4 Address Trap Reset
attempt be made to fetch an instruction from the on-chip RAM (while WDTCR1<ATAS> is “1”) or the SFR
area, address trap reset will be generated.
hardware is reset. The reset time is maximum 24/fc [s] (1.5 µs @ fc = 16.0 MHz).
While WDTCR1<ATOUT> is “1”, if the CPU should start looping for some cause such as noise and an
When an address trap reset request is generated, the
Note:When an address trap reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-fre-
quency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccura-
cies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate
value because it has slight errors.
Page 63
RESET
pin outputs a low-level signal and the internal
TMP86C847IUG

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