r2j20656anp Renesas Electronics Corporation., r2j20656anp Datasheet - Page 11

• Manufacturer Part Number: r2j20656anp
• Description: Integrated Driver - Mos Fet Drmos
• Manufacturer: Renesas Electronics Corporation.

R2J20656ANP
Description of Operation
The DrMOS multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a
single QFN package. Since the parasitic inductance between each chip is extremely small, the module is highly suitable
for use in buck converters to be operated at high frequencies. The control timing between the high-side MOS FET, low-
side MOS FET, and driver is optimized so that high efficiency can be obtained at low output-voltage.
VCIN & DISBL#
The VCIN pin is connected to the UVL (under-voltage lockout) module, so that the driver is disabled as long as VCIN
is 4.3 V or less. On cancellation of UVL, the driver remains enabled until the UVL input is driven to 3.8 V or less. The
signal on pin DISBL# also enables or disables the circuit.
Voltages from –0.3 V to VCIN can be applied to the DISBL# pin, so on/off control by a logic IC or the use of a resistor,
etc., to pull the DISBL# line up to VCIN are both possible.
The pulled-down MOS FET, which is turned on when internal IC temperature becomes over thermal shutdown level, is
connected to the DISBL# pin. The detailed function is described in THDN section.
PWM & ZCD_EN#
The PWM pin is the signal input pin for the driver chip. The input-voltage range is –0.3 V to (VCIN + 0.3 V). When the
PWM input is high, the gate of the high-side MOS FET (GH) is high and the gate of the low-side MOS FET (GL) is
low.
The ZCD_EN# pin is the Zero Current Detection Operation Enable pin for "Diode Emulation Mode (DEM)" when
ZCD_EN# is low. This function improves light load efficiency by preventing negative inductor current from output
capacitor. Driver IC monitors inductor current and when inductor current crosses zero, driver IC turn off Low side MOS
FET automatically.
Figure 1.1 shows the Typical high side and low side gate switching and Inductor current (IL) during Continuous
Conduction Mode (CCM), and figure 1.2 shows DEM when asserting Zero Current Detection Enable signal.
ZCD_EN# pin is internally pulled up to VCIN with 160 k resistor. When Zero current detection function is not used,
keep this pin open or pulled up to VCIN.
R07DS0201EJ0100 Rev.1.00
Jan 25, 2011
PWM
VCIN
H
H
H
H
L
L
CCM Operation (ZCD_EN# = "H" or Open mode)
IL
PWM
GH
GL
DISBL#
Open
GH
H
H

L
L
Disable (GL, GH = L)
Disable (GL, GH = L)
Active
Disable (GL, GH = L)
GL
H
L
Driver State
Figure 1.1 Typical Signals during CCM
Page 11 of 15
Preliminary