ncp367 ON Semiconductor, ncp367 Datasheet - Page 8

• Manufacturer Part Number: ncp367
• Description: Ncp367 Battery Charge Front-end Protection, Usb And Ac/dc Supply Compliant
• Manufacturer: ON Semiconductor

V
connection of the Li ion battery pack allows preventing
overvoltage transient, greater than 4.35 V. In case of wrong
charger conditions, the PMOS is then opened, eliminating
Battery pack over voltage which could create safety issues
and temperature increasing.
prevent voltage transients on the Battery voltage. If the
battery over voltage condition exceeds deglitch time, the
charge path is opened and FLAG pin is tied to low level
until the V
charged, V
to be recharged (4.2 V typ − 4.1 V min).
Internal PMOS FET
systems,
over-voltage. Regarding electrical characteristics, the
R
V
BAT
out
DSon
100
The connection of the V
The 4.35 V comparator has a 150 mV built-in hysteresis.
More of that, deglitch function of 2 ms is integrated to
At wall adapter insertion, and if the battery is fully
NCP367 includes an internal PMOS FET to protect the
90
80
70
60
50
40
30
20
pin versus V
Figure 13. Typical R
−50
Sense
, during normal operation, will create low losses on
BAT
bat
connected on OUT pin, from positive
−25
comparator stays locked until battery needs
is greater than 4.35 V – hysteresis.
240
220
200
180
160
140
120
100
80
in
, thanks to very low R
0
0
TEMPERATURE (°C)
DS(on)
25
100
BAT
versus Temperature
50
Theta JA curve with PCB cu thk 1.0 oz
Theta JA curve with PCB cu thk 2.0 oz
Power curve with PCB cu thk 2.0 oz
Power curve with PCB cu thk 1.0 oz
pin to the positive
200
COPPER HEAT SPREADER AREA
DSon
75
.
100
300
http://onsemi.com
(mm
125
2
)
8
400
and battery connection, with a 200 kW recommended
value.
PCB Recommendations
nevertheless PCB layout rules must be respected to
properly evacuate the heat out of the silicon. The DFN
PAD1 corresponds to the PMOS drain so must be connected
to OUT plane to increase the heat transfer. Of course, in any
case, this pad shall be not connected to any other potential.
DFN 2.2x2 mm.
ESD Tests
1 mF mounted on board). That means, in Air condition, Vin
has a ±15kV ESD protected input. In Contact condition, Vin
has ±8kV ESD protected input. Please refer to Figure 14 to see
the IEC 61000-4-2 electrostatic discharge waveform.
A serial resistor has to be placed in series with Vbat pin
The NCP367 integrates low R
Following figure shows package thermal resistance of a
NCP367 fully support the IEC61000-4-2, level 4 (Input pin,
Figure 14. IEC 61000-4-2 Electrostatic Discharge
500
T_ambient
25°C
600
700
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
DS(on)
PMOS FET,