ncp3121 ON Semiconductor, ncp3121 Datasheet - Page 35

• Manufacturer Part Number: ncp3121
• Description: Dual 3.0 A, Step-down Dc/dc Switching Regulator
• Manufacturer: ON Semiconductor

Loop Compensation
used to compensate the regulation control system. Standard
COMP pin values are shown in the BOM at the end of the
datasheet. (See the COMPCALC program to determine
customer preferred values.)
not described in Table 6 and/or for tuning the compensation
Thermal Considerations
safeguard the device from overheating when the die
temperature exceeds 160_C. For the best thermal
performance, wide copper traces and a generous amount of
PCB printed circuit board copper should be used in the board
layout. One exception to this is at the SW switching node,
which should not have a large area in order to minimize the
EMI radiation and other parasitic effects. Large areas of
copper provide the best transfer of heat from the IC into the
ambient air.
PCB Layout Guidelines
circuit board is very important. Rapidly switching currents
associated with wiring inductance, stray capacitance and
parasitic inductance of the printed circuit board traces can
generate
electromagnetic interferences (EMI) and affect the desired
operation. To minimize inductance and ground loops, the
lengths of the leads indicated by heavy lines should be kept
as short as possible. For best results, single-point grounding
or ground plane construction should be used. On the other
hand, the PCB area connected to the SW pin (drain of the
internal switch) of the circuit should be kept to a minimum
in order to minimize coupling to sensitive circuitry. Another
sensitive part of the circuit is the feedback. It is important to
keep the sensitive feedback wiring short. To ensure this,
physically locate the programming resistors near the
regulator.
under the IC with an exposed area for connecting the IC
exposed pad. Any internal ground planes should be
connected by vias to this ground area. Additional vias must
be used at the ground side of the input and output capacitors.
The GND pin also should be tied to the PCB ground in the
area under the IC.
Table 6. Compensation Values Example for Typical Output Voltages
Vin [V]
A COMP pin of the transconductance error amplifier is
To design the compensation components for conditions
The NCP3121 has thermal shutdown protection to
As in any switching regulator, the layout of the printed
There should be a ground area on the top layer directly
12
12
5
Vout [V]
voltage
3.3
1.8
5
Freq [kHz]
transients
200
200
200
Iout [A]
3
3
3
that
L11 [mH]
can
15
22
10
generate
http://onsemi.com
C11 - ceramic [mF]
NCP3121
22
22
22
35
for specific requirements, the COMPCALC design tool is
available from ON Semiconductor at no charge. Visit
http://www.onsemi.com/pub/Collateral/COMPCALC.ZIP
to download the self-extracting program for NCP3121 loop
compensation design assistance. There is an Excel design
tool for component selection. This design tool is available at
http://www.onsemi.com/.
board, the following checklist should be used to ensure
proper operation of the circuit:
When laying out the buck regulator on a printed circuit
10. Place the V
12. The exposed pad must be connected to a ground
11. Place the RT resistor as close as possible to the RT
1. Rapid changes in voltage across parasitic
2. Keep high currents out of sensitive ground
3. Avoid ground loops, as they pick up noise. Use
4. For high power buck regulators on double-sided
5. Even though double-sided PCBs are usually
6. Keep the inductor switching node small by placing
7. Use fewer, but larger, output capacitors; keep the
8. Place the output capacitors as close to the output
9. Place the COMP capacitor as close as possible to
capacitors and abrupt changes in current in
parasitic inductors are major concerns for a good
layout.
connections.
star or single-point grounding.
PCBs, a single ground plane (usually the bottom)
is recommended.
sufficient for a good layout, four layer PCBs
represent the optimum approach to reducing
susceptibility to noise. Use the two internal layers
as the power and GND planes, the top layer for
power connections and component vias, and the
bottom layer for noise sensitive traces.
the output inductor as close as possible to the chip.
capacitors clustered; and use multiple layer traces
with heavy copper to keep the parasitic resistance
low.
coil as possible.
the COMP pin.
possible to the IC.
pin.
plane with a large copper surface area to dissipate
heat.
C13 [nF]
22
18
27
R13 [kW]
IN
4.7
4.7
2.7
bypass capacitors as close as
C14 [pF]
220
270
270
R14 [W]
100
100
100
C15 [nF]
none
none
none