ncp3121 ON Semiconductor, ncp3121 Datasheet - Page 18

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ncp3121

Manufacturer Part Number
ncp3121
Description
Dual 3.0 A, Step-down Dc/dc Switching Regulator
Manufacturer
ON Semiconductor
Datasheet

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PLD devices) is drastically reduced. The failure is often a
result of high currents flowing to the pins or the high voltage
difference between pins.
supplies generating different voltage levels for core and I/O
peripherals over time. NCP3121 offers ratiometric
sequencing, sequential sequencing and tracking sections to
manage the output voltages behavior during start-up and
power-down. Basically, the DSP, FPGA, and PLD
manufacturers do not specify the method of power
sequencing, but they do specify restrictions on the time or
voltage differences during power-up and power-down. The
power-up sequence for microprocessors should be finished
approximately within a few seconds to prevent the risks
mentioned above. For more information, see the
microprocessor manufacturers' datasheets.
In that case, the signal processors require multiple power
Disable
Enable
R_TRACK
EN1
VOUT1
VOUT2
R_T
Figure 31. Ratiometric Sequencing Configuration
PG1
PG2
EN1
SEQ1
EN2
SEQ2
TRACK1
TRACK2
AVIN
GND
C3
NCP3121
http://onsemi.com
C13
R13
R23
C23
GND
C22
NCP3121
C12
18
GND
Ratiometric Sequencing
ramping at the same time and also reach the regulation level
at the same time. When common EN is pulled down, the
output voltages are going down at the same time. See Figure
31. This functionality is created by using the same capacitor
values as the soft-start capacitors for all outputs and by
connecting all EN + SEQ pins together. To ensure this
behavior, the soft start capacitors should have values greater
than the time constant of the output inductor and output
capacitor.
soft-start capacitor for both channels is not recommended.
In the ratiometric sequencing mode, multiple outputs start
For proper operation in this mode, using a common
SW1
SW2
VIN
VIN
VIN
VIN
VIN
VIN
GND
C1
D11
D21
GND
GND
GND
L21
L11
VIN
C2
GND
R12
R21
R22
R11
GND
GND
C11
C21
GND
GND
OUT1
OUT2

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