lm27241 National Semiconductor Corporation, lm27241 Datasheet - Page 2

• Manufacturer Part Number: lm27241
• Description: Synchronous Buck Regulator Controller For Mobile Systems
• Manufacturer: National Semiconductor Corporation

www.national.com
Connection Diagram
Ordering Information
Pin Description
Pin 1, VDD: 5V supply rail for the control and logic sections.
For normal operation the voltage on this pin must be brought
above 4.5V. Subsequently, the voltage on this pin (including
any ripple component) should not be allowed to fall below 4V
for a duration longer than 7µs. Since this pin is also the
supply rail for the internal control sections, it should be
well-decoupled particularly at high frequencies. A minimum
0.1µF-0.47µF (ceramic) capacitor should be placed on the
component side very close to the IC with no intervening vias
between this capacitor and the VDD/SGND pins. If the volt-
age on Pin 1 falls below the lower UVLO threshold, upper
FET(s) are latched OFF and the lower FET(s) are latched
ON. Power Not Good is then signaled immediately (on Pin
6). To initiate recovery, the EN pin must be taken below 0.8V
and then back above 2V (with VDD held above 4.5V). Or the
voltage on the VDD pin must be taken below 1.0V and then
back again above 4.5V (with EN pin held above 2V). Normal
operation will then resume assuming that the fault condition
has been cleared.
Pin 2, SS: Soft-start pin. A Soft-start capacitor is placed
between this pin and ground. A typical capacitance of 0.1µF
is recommended between this pin and ground. The IC con-
nects an internal 1.8 kΩ resistor (R
Characteristics table) between this pin and ground to dis-
charge any remaining charge on the Soft-start capacitor
under several conditions. These conditions include the initial
power-up sequence, start-up by toggling the EN pin, and
also recovery from a fault condition. The purpose is to bring
down the voltage on the Soft-start pin to below 100mV for
obtaining reset. Reset having thus been obtained, an 11µA
current source at this pin charges up the Soft-start capacitor.
The voltage on this pin controls the maximum duty cycle,
and this produces a gradual ramp-up of the output voltage,
thereby preventing large inrush currents into the output ca-
pacitors. The voltage on this pin finally clamps close to 5V.
This pin is connected to an internal 115µA current sink
whenever a current limit event is in progress. This sink
LM27241MTCX
Order Number
LM27241MTC
SS_DCHG
, see Electrical
20-Lead TSSOP (MTC)
Package Drawing
Top View
MTC20
MTC20
2
current discharges the Soft-start capacitor and forces the
duty cycle low to protect the power components. When a
fault condition is asserted (See Pin 9) the SS pin is internally
connected to ground via the 1.8 kΩ resistor.
Pin 3, FREQ: Frequency adjust pin. The switching frequency
is set by a resistor connected between this pin and ground.
A value of 22.1kΩ sets the frequency to 300kHz (nominal). If
the resistance is increased, the switching frequency de-
creases. An approximate relationship is that for every 7.3kΩ
increase or decrease in the value of the frequency set resis-
tor, the total switching period increases or decreases by 1µs.
Pin 4, SGND: Signal Ground pin. This is the lower rail for the
control and logic sections. SGND should be connected on
the PCB to the system ground, which in turn is connected to
PGND. The layout is important and the recommendations in
the section Layout Guidelines should be followed.
Pin 5, EN: IC Enable pin. When EN is taken high, the output
is enabled by means of a Soft-start power-up sequence.
When EN is brought low, Power Not Good is signaled within
100ns. This causes Soft-shutdown to occur (see Pins 2 and
6). The Soft-start capacitor is then discharged by an internal
1.8kΩ resistor (R
table). When the Enable pin is toggled, a fault condition is
not asserted. Therefore in this case, the lower FET is not
latched ON, even as the output voltage ramps down, even-
tually falling below the under-voltage threshold. In fact, in
this situation, both the upper and the lower FETs are latched
OFF, until the Enable pin is taken high again. If a fault
shutdown has occurred, taking the Enable pin low and then
high again (toggling), resets the internal latches, and the IC
will resume normal switching operation.
Pin 6, PGOOD: Power Good output pin. An open-drain logic
output that is pulled high with an external pull-up resistor,
indicating that the output voltage is within a pre-defined
Power Good window. Outside this window, the pin is inter-
nally pulled low (Power Not Good signaled) provided the
output error lasts for more than 7µs. The pin is also pulled
low within 100ns of the Enable pin being taken low, irrespec-
20120102
SS_DCHG
2500 Units/13" Reel
Supplied As
73 Units/Rail
, see Electrical Characteristics